Interconnections having double capping layer and method for...

Details Interconnections having double capping layer and method for... Interconnections having double capping layer and method for...

2007-04-17

2007-04-17

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S760000

Reexamination Certificate

active

11367790

ABSTRACT:
Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

REFERENCES:
patent: 6465888 (2002-10-01), Chooi et al.
patent: 6656840 (2003-12-01), Rajagopalan et al.
patent: 6737747 (2004-05-01), Barth et al.
patent: 6756321 (2004-06-01), Ko et al.
patent: 6873057 (2005-03-01), Chen et al.

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