Interconnection with self-aligned via plug

Details Interconnection with self-aligned via plug Interconnection with self-aligned via plug

1996-01-04

1997-01-21

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257773, 257776, 257752, H01L 23485, H01L 23532

Patent

active

055962300

ABSTRACT:
A device and a method of formation on a substrate of a semiconductor interconnection via structure for semiconductor devices is provided. Initially, form a first metal layer on the substrate, a first dielectric layer upon the first metal layer, and a mask upon the dielectric layer with a metal etching pattern therein. Then, etch through the first dielectric layer and the first metal layer to the substrate forming trenches between metal lines formed from the first metal layer covered with the dielectric layer. Next, form a first etch stop layer upon the surface of the the first dielectric layer and planarize it, a second dielectric layer above the etch stop layer, and a second etch stop layer on the second dielectric layer. Then, pattern the second dielectric and the second etch stop layer and etch to form a via hole down to a surface of the first metal layer. Then, form a second metal layer and a metal plug in the via hole extending into contact with the first metal layer.

REFERENCES:
patent: 5117276 (1992-05-01), Thomas et al.
patent: 5155576 (1992-10-01), Mizushima
patent: 5189506 (1993-02-01), Cronin et al.
patent: 5396092 (1995-03-01), Peek
patent: 5442236 (1995-08-01), Fukazawa
K. Ueno et al, "Quarter-Micron Planarized Interconnection Technology with Self-Aligned Plug", IEDM '92, 305-307.

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