Interconnection with metal plug and reduced step

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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Details

257763, 257770, 257774, H01L 2348, H01L 2352

Patent

active

057866376

ABSTRACT:
After an interconnection layer of Al alloy or the like is formed on an insulating film covering the surface of a substrate, a contact hole is formed through a laminate of the insulating film and connection layer at the position corresponding to a connection part of the substrate. After the interconnection layer is patterned, an adhesion layer of TiN or the like is formed on the insulating film, covering a left portion of the interconnection layer and the inner surface of the contact hole. A conductive layer of W or the like is formed on the adhesion layer by blanket CVD, burying the contact hole. Thereafter, the conductive layer and adhesion layer are etched back to form an interconnection 22 including the left portion of the interconnection layer, left portions of the adhesion layer, and left portions of the conductive layer. A step of the interconnection can be relieved by leaving the portions of the conductive layer on the side walls of the interconnection.

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M. Sato, Et Al., "Supperssion of Microloading Effect by Low-Temperature SiO.sub.2 Etching", Jpn. J. Appl. Phys., vol. 31 (1992), pp. 4370-4375.

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