Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Patent
1987-11-23
1989-10-10
Abrams, Neil
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
361394, 361395, H01R 909
Patent
active
048728438
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to interconnection systems for electrical circuits and, more particularly, to systems which enable electrical circuits to be laid out in three dimensions.
GB-B-2 095 039 and -2 127 217 both describe assemblies for connecting together a number of electrical component packages which carry electrical circuit components. Since these electrical circuit components are normally semiconductor chips, these packages, which typically, but not necessarily, carry only a single chip, will be referred to herein as "chip carriers". In both these references, electrical interconnections between the chip carriers are made by mounting the carriers into a rack which also acts as the support structure. It is also proposed in GB-B-2 127 217 to provide electrical connections between adjacent chip carriers by means of a spacer element mounted between each adjacent pair of chip carriers. Such a spacer element does not, however, provide mechanical support for the assembly of chip carriers, and an external rack or similar is still required. The use of a rack, which is typically fabricated from strips of material of a predetermined length, restricts the number of chip carriers which can be assembled together, and therefore the overall size of a circuit which can be produced using this existing system.
GB-A-2 145 571 describes a system for stacking together printed circuit boards separated by spacer elements. It is proposed to hold the stack together by adhesives, clipping or by the use of an external framework. It is stated in this reference that for stability reasons the maximum length of a stack produced with this system may be limited to as little as twice the largest dimension of the board. This therefore limits the size of circuit that can be constructed with this system.
Another technical problem associated with the use of a rack or spacer elements to connect a number of chip carriers, is that all the power and signal connections for each carrier must be passed across each preceding chip carrier. Since all the chip carriers will draw some power from the power line, there will be a resultant loss in the potential available for the chip carriers most remote from the source of power, possibly leading to a failure of the electrical components on the chip carriers to operate correctly. In the case of signals which must be passed from a chip on one carrier to a chip which is not directly adjacent, or which must be passed to several such chips, the level of the signal can be reduced in its transition across each chip carrier, again leading to possible failures of the circuit to operate correctly.
The technical problem underlying the present invention is that of providing a versatile system of interconnecting a large number of chip carriers in conjunction with providing a mechanism within such a system of distributing power and signals to individual carriers without incurring unacceptable levels of power or signal level loss.
The present invention accordingly provides an interconnection system comprising a plurality of stackable spacers each having means for mechanically interlocking with adjacent spacers in order to define an elongate stack in which apertures are defined through the faces thereof between adjacent spacers.
These spacers can be adapted to form stacks in which chip carriers are clamped between adjacent spacers, and wherein portions of the spacer defining edges of the apertures are provided with electrical connection means for co-operating with corresponding electrical connection means on the chip carriers. Preferably such spacers are frame shaped rectangular members with side portions, the upper and lower surfaces of which are adapted to define, together with respective facing surfaces of a side portion of an adjacent carrier, the edges of an aperture through each of the four faces of the stack between each adjacent pair of spacers, chip carriers being clampable between the side portions of adjacent spacers.
In order to provide for power and signal transmission, spacers are used which have a
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patent: 3212047 (1965-10-01), McDonough
patent: 3239719 (1966-03-01), Shower
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patent: 4162818 (1979-07-01), Martin
patent: 4395084 (1983-07-01), Conrad
patent: 4688074 (1987-08-01), Iinuma
patent: 4688864 (1987-08-01), Sorel
patent: 4692790 (1987-09-01), Oyamada
Abrams Neil
Dowty Electronic Components Limited
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