Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-12-14
2004-12-07
Baumeister, Bradley (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S673000, C257S690000, C257S700000, C257S758000, C257S737000, C438S613000, C438S629000, C438S637000, C438S639000, C438S640000, C361S760000, C361S784000, C361S792000, C361S794000, C174S250000, C174S260000, C428S901000, C029S830000
Reexamination Certificate
active
06828669
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an interconnection substrate and a manufacturing method thereof and, more particularly, to an interconnection substrate and a manufacturing method thereof which are useful in reducing stress that occurs between the interconnection substrate and a semiconductor element mounted thereon.
2. Description of the Related Art
Recently, as electronic machines have shrunk in size, semiconductor devices mounted thereon have also been miniaturized. One of these miniaturized semiconductor devices is a CSP (Chip-Size Package). The CSP (hereinafter referred to as semiconductor package) is a multilayer interconnection substrate on which semiconductor elements such as an LSI chip are directly mounted by solder bumps or pins.
FIG. 1A
is a cross-sectional view of the conventional semiconductor package.
FIG. 1A
shows a multilayer interconnection substrate
101
and a semiconductor element
105
to be mounted thereon. As shown in the figure, the semiconductor element
105
has electrodes
107
. Each of the electrodes
107
has a column
106
composed of conductive metals. The column
106
has a solder bump
104
on its end. A resin layer
103
protects water penetrating to the semiconductor element
105
.
The multilayer interconnection substrate
101
has terminal pads
102
in its uppermost layer. The above-mentioned semiconductor element
105
is then mounted on the multilayer interconnection substrate
101
so that the solder bump
104
is welded to each of the terminal pads
102
with pressure. Thereafter, by reflowing the solder bump
104
, the semiconductor element
105
is electrically and mechanically connected to the multilayer interconnection substrate
101
.
FIG. 1B
is a cross-sectional view of the multilayer interconnection substrate
101
and the semiconductor element
105
mounted thereon in the above-mentioned manner.
Generally, the multilayer interconnection substrate
101
and the semiconductor element
105
have different coefficients of thermal expansion. Thus, the multilayer interconnection substrate
101
and the semiconductor element
105
undergo different amounts of thermal contraction during cooling down after the reflowing of the solder bump
104
. Two arrows in
FIG. 1B
indicate the amounts and directions of the thermal contraction which the multilayer interconnection substrate
101
and the semiconductor element
105
undergo.
The above-mentioned column
106
relaxes stress which is caused by the different amounts of thermal contraction of the multilayer interconnection substrate
101
and the semiconductor element
105
and acts therebetween. A description will be given, with reference to
FIG. 2
, of this point.
FIG. 2A
is a cross-sectional view of the column
106
immediately after mounting the semiconductor element
105
and reflowing the solder bump
104
. At this point, the whole body is still at a high temperature, and the multilayer interconnection substrate
101
and the semiconductor element
105
have not started thermal contraction yet.
FIG. 2B
is a cross-sectional view of the column
106
quite a long time after mounting the semiconductor element
105
and reflowing the solder bump
104
. In this figure, the multilayer interconnection substrate
101
and the semiconductor element
105
have undergone thermal contraction. The different amounts of thermal contraction of the multilayer interconnection substrate
101
and the semiconductor element
105
have resulted in stress, which has made the column
106
inclined, as shown in FIG.
2
B.
The inclining metal column
106
relaxes the stress which acts on the solder bump
104
. Therefore, this prevents the stress from separating the solder bump
104
from the terminal pad
102
provided on the multilayer interconnection substrate
101
. This also prevents the stress from acting on and cracking the semiconductor element
105
.
The above-mentioned column
106
is formed on the semiconductor element
105
in a post-process thereof, that is, after a pre-process of manufacturing the semiconductor element
105
.
However, forming the column
106
in the post-process prolongs the duration of the post-process to that extent. This increases the possibility of the semiconductor element
105
, which is completed in itself in the pre-process, falling inferior in the prolonged post-process and, thus, decreases the yield rate of the costly semiconductor elements.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved and useful interconnection substrate and a manufacturing method thereof in which the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide an interconnection substrate having metal columns covered by a resin film and a manufacturing method thereof which can relax stress, caused originally by different coefficients of thermal expansion between a multilayer interconnection substrate or the interconnection substrate and the semiconductor element mounted thereon, not on the side of the semiconductor element, but on the side of the substrate.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a multilayer interconnection substrate comprising:
an uppermost interconnection layer having a plurality of terminal pads formed at positions corresponding to a plurality of external connection terminals provided on a semiconductor element which is to be mounted on the multilayer interconnection substrate;
a metal column formed on each of the terminal pads;
a resin film covering a side surface of the metal column; and
an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.
Additionally, in the present invention, a height of the metal column may be smaller than a thickness of the insulating layer.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a multilayer interconnection substrate manufacturing method comprising the steps of:
forming a plurality of terminal pads in an uppermost interconnection layer;
forming an insulating layer on the uppermost interconnection layer;
forming openings in the insulating layer, the openings located at positions corresponding to the terminal pads;
filling each of the openings with metal particles;
forming a metal column in each of the openings by heating the metal particles at a temperature which melts the metal particles; and
removing a part of the insulating layer near but not adjacent to a peripheral side of the metal column, while leaving a part of the insulating layer adjacent to the peripheral side of the metal column, so that a gap is formed around but not adjacent to the peripheral side of the metal column.
Additionally, in the present invention, the step of filling may include a step of filling each of the openings with the metal particles up to a predetermined level in the middle of each of the openings.
In order to achieve the above-mentioned objects, there is also provided according to still another aspect of the present invention a multilayer interconnection substrate manufacturing method comprising the steps of:
forming a plurality of terminal pads in an uppermost interconnection layer;
forming an insulating layer on the uppermost interconnection layer;
forming openings in the insulating layer, the openings located at positions corresponding to the terminal pads;
forming a conductive layer on surfaces of the insulating layer and inner surfaces of the openings;
forming a plating metal on the conductive layer by electrolytic plating by using the conductive layer as an electric supply layer so that the plating metal fills the openings;
forming a metal column in each of the openings by removing other parts of the conductive layer and the plating metal than a part formed in each of the openings by one of etching and polishing so that the conducti
Iijima Takahiro
Matsuda Yuichi
Wakabayashi Shinichi
Baumeister Bradley
Chu Chris C.
Ladas & Parry
Shinko Electric Industries Co. Ltd.
LandOfFree
Interconnection substrate having metal columns covered by a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interconnection substrate having metal columns covered by a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnection substrate having metal columns covered by a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3287080