Interconnection substrate and semiconductor device,...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S762000, C257SE23145, C257SE21585, C438S256000

Reexamination Certificate

active

08080875

ABSTRACT:
An interconnection substrate including therein one or more resin layers, each of the resin layers including therein a via-hole penetrating from a top surface to a bottom surface of the resin layer. A via-plug of metal particles is formed in the via-hole. Each of the metal particles has a flattened shape generally parallel to a plane of the resin layer.

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patent: 2006147734 (2006-06-01), None
Akedo, Jun “Aerosol Deposition of Ceramic Thick Films at Room Temperature: Densification Mechanism of Ceramic Layers”, J. Am Ceram. Soc. 89 (6) Jun. 2006, pp. 1834-1839.
“JP Official Action”, mailed by JPO and corresponding to Japanese application No. 2007-038199 on Jul. 19, 2011, with partial English translation.

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