Interconnection structure of semiconductor integrated circuit de

Details Interconnection structure of semiconductor integrated circuit de Interconnection structure of semiconductor integrated circuit de

1994-03-15

1996-01-30

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437194, 437247, H01L 2144, H01L 2148

Patent

active

054880149

ABSTRACT:
A surface of a first aluminum interconnection layer in a connection hole is exposed to a plasma of oxygen or fluorine-containing gas during the forming step of the connection hole. In order to remove the thin deterioration layer which forms as a result, sputter etching is effected by an argon ion. There are residual particles of the oxide and fluoride of aluminum on the surface of the first aluminum interconnection layer. A titanium layer is formed on the insulating layer to be in contact with the surface of the first aluminum layer through the through hole. A titanium compound layer is formed on the titanium layer. A second aluminum layer is formed on the titanium compound layer. A heat treatment is effected to decompose the residual particles and to form an intermetallic compound (TiAl.sub.3).

REFERENCES:
patent: 4410622 (1983-11-01), Dalal et al.
patent: 4710398 (1987-12-01), Homma et al.
patent: 4751198 (1988-06-01), Anderson
patent: 4910580 (1990-03-01), Kuecher et al.
patent: 4917759 (1990-04-01), Fisher et al.
patent: 4924295 (1990-05-01), Kuecher
patent: 4937652 (1990-06-01), Okumura et al.
patent: 4962414 (1990-10-01), Liou et al.
patent: 4985750 (1991-01-01), Hoshing
patent: 4987562 (1991-01-01), Watanabe
patent: 5008730 (1991-04-01), Hunng et al.
patent: 5049975 (1991-09-01), Ajika et al.
patent: 5051812 (1991-09-01), Onuki et al.
patent: 5070392 (1991-12-01), Coffey et al.
patent: 5081064 (1992-01-01), Inoue et al.
patent: 5200359 (1993-04-01), Pearey et al.
patent: 5231053 (1993-07-01), Bost et al.
patent: 5308793 (1994-05-01), Toguchi et al.
patent: 5312775 (1994-05-01), Fujii et al.
patent: 5313101 (1994-05-01), Harada et al.
patent: 5356836 (1994-10-01), Chen et al.
patent: 5358901 (1994-10-01), Fiordalice et al.
"High Performance Multilevel Interconnection System with Stacked interlayer Dielecticfs by Plasma CVD and Blast Sputtering", M. Abe et al, pp. 404-410, VIMC Conference, 1989.
"A New Reliability Problem Associated with Ar Ion Sputter Cleaning of Interconnect Vias", H. Tomioka et al, IEEE/IRPS, 1989, pp. 53-58.
"Multilevel Interconnection for Half-Micron VLSI's", T. Nishida et al, VIMC Conference, 1989, pp. 19-25.

Affiliated with

Also associated with

Rating

Interconnection structure of semiconductor integrated circuit de does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interconnection structure of semiconductor integrated circuit de, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnection structure of semiconductor integrated circuit de will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-156513