Interconnection structure of a semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays

Reexamination Certificate

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Details

C257S206000, C257S210000, C257S211000, C257S774000, C257S907000, C257S908000

Reexamination Certificate

active

06876014

ABSTRACT:
Concave portions and convex portions are formed on an insulating layer. First bit lines are arranged on the convex portions. A width of the first bit lines is set to L, and a space between the first bit lines is set to L+2S. Each of the first bit lines is electrically connected to a drain diffusion layer by a contact plug. Second bit lines are arranged in a trench between the first bit lines. A width of the second bit lines is set to L, and a space between the first and second bit lines is equal to a width S of a side wall. Each of the second bit lines is electrically connected to a drain diffusion layer by a contact plug.

REFERENCES:
patent: 5837577 (1998-11-01), Cherng
patent: 6214662 (2001-04-01), Sung et al.
patent: 6255160 (2001-07-01), Huang
patent: 6353269 (2002-03-01), Huang
patent: 6-338597 (1994-12-01), None
patent: 8-153859 (1996-06-01), None
patent: 2000-501886 (2000-02-01), None

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