Interconnection structure in semiconductor device and manufactur

Details Interconnection structure in semiconductor device and manufactur Interconnection structure in semiconductor device and manufactur

1988-03-15

1989-10-03

LaRoche, Eugene R.

357 68, H01L 2952, H01L 2348, H01L 2944, H01L 2962

Patent

active

048720500

ABSTRACT:
Conductive layers (5a, 9a) included in a multi-layer structure (30a) are electrically interconnected through a conductive connection wall (13a) provided in a contact hole (12) and contacting the side surface (22) of the multi-layer structure (30a). The upper conductive layer (11a) existing on the multi-layer structure (30a) and the lower conductive layer (3) exisitng under the multi-layer structure (30a) are electrically interconnected through a conductive film (11b) provided in the contact hole (12). These two interconnections are insulated from each other by an insulating film (18) provided on the connection wall (13a).

REFERENCES:
patent: 4239346 (1980-12-01), Lloyd
patent: 4265935 (1981-05-01), Hall
patent: 4413272 (1983-11-01), Mochizuki et al.
patent: 4641170 (1987-02-01), Ogura et al.
patent: 4712125 (1987-12-01), Bhatia et al.
patent: 4731341 (1988-03-01), Kawakatsu
"A VLSI Biopolar Metallization Design . . . ", IBM J. Res. Develop., vol. 26, No. 3, May 1982, pp. 362-371.
"VLSI Multilevel Metallization", Solid State Technology, Dec. 1984, pp. 93-100.

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