Interconnection structure in semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

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Details

257736, 257752, 257753, 257756, 257923, H01L 2348, H01L 2946, H01L 2954

Patent

active

052851109

ABSTRACT:
An interconnection structure of a semiconductor device for electrically connecting a thin conductive layer and a metallization and the fabrication method thereof are disclosed. The interconnection structure includes a semiconductor substrate, an insulating layer coated on the substrate, a thick conductive layer formed on a certain portion of the insulating layer, a first interlaid insulating layer covering the thick conductive layer, a first contact hole formed within the first interlaid insulating layer on the thick conductive layer, a thin conductive layer consisting of vertical structure formed in the first contact hole and horizontal structure formed on the first interlaid insulating layer, a second interlaid insulating layer covering the thin conductive layer, a second contact hole formed within said first and second interlaid insulating layers and crossing the first contact hole, and a metallization filling the second contact hole and formed on the second interlaid insulating layer. Thus, the contact area between the metallization and thin conductive layer is increased, thereby allowing a reliable ohmic contact while directly connecting the thin conductive layer and metallization.

REFERENCES:
patent: 4922321 (1990-05-01), Arai et al.
patent: 4961104 (1990-10-01), Hirakawa

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