Interconnection structure for conductive layers

Details Interconnection structure for conductive layers Interconnection structure for conductive layers

1994-08-05

1995-04-18

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257774, 257769, 257754, 257750, H01L 2348, H01L 2946, H01L 2962

Patent

active

054081300

ABSTRACT:
An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).

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"A Split Wordline Cell for 16Mb SRAM Using Polysilicon Sidewall Contacts," by Itabashi et al., published via IEDM 1991, pp. 477-480.

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