Interconnection structure and methods

Details Interconnection structure and methods Interconnection structure and methods

2002-04-02

2003-12-09

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S103000, C365S105000

Reexamination Certificate

active

06661691

ABSTRACT:

FIELD OF THE INVENTION
This application relates to interconnection structures especially useful in semiconductor devices such as integrated circuits and memory devices and relates to methods for fabricating and using such structures.
BACKGROUND ART
Integrated circuits including arrays of memory nodes or logic gates have increased steadily in density. Such integrated circuits have included dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, programmable read-only memory (PROM) integrated circuits, electrically erasable programmable read-only memory (EEPROM) integrated circuits, write-once read-many (WORM) memory devices, and logic devices such as programmable logic array (PLA) integrated circuits, among others. Integrated circuits having arrays of devices, gates, or memory nodes disposed on multiple levels require “vertical” interconnections or “pillars” to interconnect devices, gates, or memory nodes on one level with other devices, gates, or nodes on other levels. In this context, the term “vertical” differs from its everyday connotation in that it does not refer to the direction of gravity. Throughout this specification, the drawings, and the appended claims, the term “vertical” refers to a direction generally perpendicular to a substrate or base plane of an integrated circuit. Also, the term “pillar” referring to an interconnection and the term “vertical interconnection” are used interchangeably to mean an interconnection communicating between different layers of an integrated circuit, regardless of the spatial orientation of those different layers. Integrated circuits herein include not only monolithic integrated circuits, but also hybrid integrated circuits and multi-layer or “stacked” modules. The term “cell” herein refers to a functional element of an array, such as a memory node, a logic gate, a switching device, a field-effect device, or a semiconductor device.
There is a continuing need for increased device density in integrated circuits, including multi-layer integrated circuits and for efficient interconnection structures within such multi-layer integrated circuits.


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