Interconnection structure and method for designing the same

Details Interconnection structure and method for designing the same Interconnection structure and method for designing the same

2002-03-20

2004-03-23

Trinh, Michael (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S760000, C257S522000, C438S926000, C438S619000

Reexamination Certificate

active

06710449

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an interconnection structure and a method for designing the same in a semiconductor integrated circuit device with an interconnection structure incorporating air gaps.
Recently, as semiconductor integrated circuits have been miniaturized, the operating speed of transistors has improved, and RC delay time of interconnection has occupied the majority of signal processing time. Accordingly, reduction of wire-to-wire capacitance is most effective in reducing the RC delay, which increases as the wire length is increased and the wiring is miniaturized. In addition, as a semiconductor integrated circuit device has been more densely integrated, the capacitance between wires disposed horizontally to a substrate has been rapidly increased as compared to the capacitance between wires disposed perpendicularly to the substrate. Specifically, the shrinkage rate of a horizontal wire-to-wire space is different from that of a perpendicular wire-to-wire space. If the design rule is reduced by one generation, the wire-to-wire space and the wire width are generally reduced to about 60-70% horizontally and to about 90% perpendicularly. Thus, the more the circuit is miniaturized, the wider the difference of the wire-to-wire spaces between the horizontal and perpendicular directions become. As a result, to suppress the increase in wire-to-wire capacitance caused by miniaturization of the semiconductor integrated circuit, techniques for reducing the dielectric constant between wires are needed.
As a known technique, a semiconductor integrated circuit with an interconnection structure incorporating air gaps that can reduce a signal delay caused by the interconnection to 40% as compared to usual techniques is being used. The interconnection structure incorporating air gaps is not a structure in which every region between wires is intentionally filled up with an insulating film, but a structure in which air gaps are formed within the insulating film by utilizing a plasma CVD film with a low coverage.
By providing such an interconnection structure incorporating air gaps to a semiconductor integrated circuit device, it is possible to reduce a real relative dielectric constant between wires significantly and also to reduce the delay time depending on the wire-to-wire capacitance to 40% as compared to usual techniques.
At present, no method for designing a semiconductor integrated circuit device suitable for the interconnection structure incorporating air gaps has been established. In the interconnection structure incorporating air gaps, if air gaps occupy too much space in each interconnect layer, the strength of the interconnection structure might not be sufficiently secured. On the other hand, in reducing the delay depending on the parasitic capacitance between wires, so long as wires are spaced apart from each other by a certain distance or more, no substantial problem occurs because the parasitic capacitance is reduced.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an interconnection structure, in which the strength thereof can be maintained and the delay depending on the parasitic capacitance between wires can be reduced. It is another object of the present invention to produce a method for designing wiring to obtain the structure.
A first inventive method for designing an interconnection structure of an interconnect layer in a semiconductor integrated circuit device, includes the steps of: a) forming a first dummy pattern so that at least part of the first dummy pattern is spaced apart from an actual wiring pattern by a distance equal to or smaller than a first value; b) combining the actual wiring pattern with at least the part of the first dummy pattern, thereby forming a final wiring pattern; and c) defining a gap in the final wiring pattern with a value equal to or smaller than the first value as an air gap region, in the interconnect layer.
According to this method, when an interconnection structure is formed using the final wiring pattern, gaps with a value equal to or smaller than the first value are turned into air gap regions. Some of these gaps are located in the actual wiring pattern, some are located in the dummy pattern, and the others are located between the actual wiring pattern and the first dummy pattern. Thus, air gap regions are created so as to surround almost the entire actual wiring pattern, and a structure incorporating air gaps in which no insulating film exists between the actual wiring pattern and the dummy pattern is formed. As a result, wire-to-wire capacitance can be suppressed.
In one embodiment of the present invention, the step a) may include the sub-steps of: a1) enlarging the actual wiring pattern by the first value, thereby forming a first enlarged wiring pattern; a2) enlarging the actual wiring pattern by a second value, which is larger than the first value, thereby forming a second enlarged wiring pattern; and a3) removing part of the second enlarged wiring pattern where the first and second enlarged wiring patterns overlap each other, thereby forming the first dummy pattern. Then, the first dummy pattern can be easily formed so that at least part of the first dummy pattern is spaced apart from the actual wiring pattern by the first value or smaller, using the enlarged patterns of the actual wiring pattern.
In another embodiment, the first inventive method may include the step a′) of forming, in the interconnect layer, a second dummy pattern at a position apart from either the actual wiring pattern or the first dummy pattern by the first value in a region where neither the actual wiring pattern nor the first dummy pattern exists, between the steps a) and b). In the step b), the actual wiring pattern and the first and second dummy patterns may be combined, thereby forming the final wiring pattern. Then, a lager number of air gap regions can be created.
In this particular embodiment, in the step a′), it is preferable that after a simple-figure pattern made of simple figures has been formed, the actual wiring pattern and the first dummy pattern are respectively enlarged by a third value, which is larger than the first value, thereby forming a third enlarged wiring pattern, and then part of the third enlarged wiring pattern where the third enlarged wiring pattern and the simple-figure pattern overlap each other is removed, thereby forming the second dummy pattern. Then, a larger number of air gap regions can be created using the simple-figure pattern.
In still another embodiment, the first inventive method may include the steps of: a″) forming a lattice dummy pattern between the steps a) and b); and a′″) forming a separated dummy pattern by separating the first dummy pattern using the lattice dummy pattern. In the step b), the separated dummy pattern, which is part of the first dummy S pattern, and the actual wiring pattern may be combined, thereby forming the final wiring pattern. Then, the parasitic capacitance between the first wiring pattern and the first dummy pattern can be reduced. As a result, the effect of suppressing a signal delay depending on the parasitic capacitance between wires can be remarkably exhibited.
In yet another embodiment, in the step a), the first dummy pattern may be formed using the first simple-figure pattern made of simple figures. Then, air gap regions can be
1
s easily created.
In this particular embodiment, the step a) preferably includes the sub-steps of: a11) forming the first simple-figure pattern; a12) enlarging the actual wiring pattern by a third value, which is larger than the first value, thereby forming a third enlarged wiring pattern; and a13) removing part of the third enlarged wiring pattern where the third enlarged wiring pattern and the first simple-figure pattern overlap each other, thereby forming the first dummy pattern. Then, the first dummy pattern can be easily formed so that at least part of the first dummy pattern is apart from the actual wiring pattern by a distance equal to or sm

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