Interconnection resource assignment method for differential curr

Details Interconnection resource assignment method for differential curr Interconnection resource assignment method for differential curr

1993-04-12

1997-07-15

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, G06F 1750

Patent

active

056489129

ABSTRACT:
A method for assigning interconnection resources to input/output connection points on differential current switch logic elements which need to use the resources, but which introduce an order dependency to the assignment problem, due to restrictions unique to differential current logic. The input/output connection points are paired first as are the interconnection resources. Pairing removes the order dependency. An assignment is then made through the use of an optimizing linear assignment algorithm suitable for single input/output connection point to single interconnection resource assignments. Preferably, a cost matrix is generated to determine the optimum assignment by minimizing the total assignment cost. The paired assignments are then broken apart to assign each individual member of the point pair to an individual member of the assigned resource pair. The final assignment of the individual pair members is compared to legality constraints, the violation of which may have been masked in the calculation of assignment costs of the pairs.

REFERENCES:
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4593363 (1986-06-01), Burstein et al.
patent: 4607339 (1986-08-01), Davis
patent: 4608649 (1986-08-01), Davis et al.
patent: 4615001 (1986-09-01), Hudgins, Jr.
patent: 4636965 (1987-01-01), Smith et al.
patent: 4742471 (1988-05-01), Yoffa et al.
patent: 4777606 (1988-10-01), Fournier
patent: 4829446 (1989-05-01), Draney
patent: 4839821 (1989-06-01), Murakata
patent: 4852015 (1989-07-01), Doyle, Jr.
patent: 4852016 (1989-07-01), McGehee
patent: 4890238 (1989-12-01), Klein et al.
patent: 4903214 (1990-02-01), Hiwatashi
patent: 4908772 (1990-03-01), Chi
patent: 4975854 (1990-12-01), Yabe
patent: 5072402 (1991-12-01), Ashtaputre et al.
patent: 5224056 (1993-06-01), Chene et al.
patent: 5237514 (1993-08-01), Curtin
patent: 5272645 (1993-12-01), Kawakami et al.
patent: 5397749 (1995-03-01), Igarashi
patent: 5457410 (1995-10-01), Ting
Yao et al., "A New Approach to the Pin Assignment Problem", IEEE Trans. on CAD, vol. 8, No. 9, pp. 990-1006, 1989.
Marek-Sadowska et al., "Pin Assignment for Improved Performance in Standard Cell Design", IEEE, pp. 339-342, 1990.
Pedram et al., "Floorplanning with Pin Assignment," IEEE, 1990, pp. 98-101.
Jingsheng Cong, "Pin Assignment with Global Routing", IEEE, 1989, pp. 302-305.
Jingsheng Cong "Pin Assignment with Global Routing" 1989 Urbana, IL.
Massoud Pedram et al. "Floorplanning with Pin Assignment" 1990 Berkeley, CA.
E.B. Eichelberger et al. "Differential Current Switch--High performance at low power" IBM Journal of Research and Development pp. 313-319, vol. 35, No. 3 May 1991.

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