Interconnection of land section to wiring layers at center...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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Details

C257S690000, C257S758000, C257S734000, C257S773000, C257S774000, C438S602000, C438S605000, C438S618000, C438S622000, C438S624000, C438S629000, C438S639000, C438S652000, C438S667000

Reexamination Certificate

active

08004077

ABSTRACT:
A semiconductor device comprising: a substrate; a terminal on the substrate's first surface; a first electrode on the first surface connected to the terminal; an electronic element on the substrate's second surface; a second electrode connected to the electronic element; a groove on the second surface leading to the second electrode; a conductive portion inside the grove connected to the second electrode's rear face; a first wiring on the first surface connected to the first electrode; a second wiring connecting the first wiring and the terminal; a stress-absorbing layer between the substrate and terminal; a land connecting the first wiring and the second wiring, the land opening a part of the stress-absorbing layer and exposing the first wiring, the land being in a region surrounded by terminals, and the land being along a straight line connecting the centers of diagonal terminals, with the region between the terminals.

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Communication from European Patent Office regarding counterpart application, Nov. 24, 2010.

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