Interconnection of elements on integrated circuit substrate

Details Interconnection of elements on integrated circuit substrate Interconnection of elements on integrated circuit substrate

1983-09-16

1986-03-11

Larkins, William D.

357 40, 357 68, 357 71, H01L 2710, H01L 2352, H01L 2952

Patent

active

045757445

ABSTRACT:
Concentric patterns of cells or macros (1) and conductive lines 13 conserve space on a substrate having two conductive levels. Macros (1) occupy only the first metal level and lines 13 are on the second metal level. The second metal level may also contain concentric patterns of power buses 20 and ground buses 20.

REFERENCES:
patent: 3199002 (1965-08-01), Martin, Jr.
patent: 3751720 (1973-08-01), Nestork
patent: 3795845 (1974-03-01), Cass et al.
patent: 3808475 (1974-04-01), Buelow et al.
patent: 4295149 (1981-10-01), Balyoz et al.
IBM Technical Disclosure Bulletin entitled "Bay Structure for Logic Chips," by K. R. King, vol. 18, No. 5, Oct. 1975, at p. 1510.

Affiliated with

Also associated with

Rating

Interconnection of elements on integrated circuit substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interconnection of elements on integrated circuit substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnection of elements on integrated circuit substrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2193646