Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2011-02-08
2011-02-08
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S012000
Reexamination Certificate
active
07886128
ABSTRACT:
A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify any source operand addresses or target operand addresses. The source operands and target operands for arithmetic/logic execution units are provided by independent load instruction operations and independent store instruction operations.
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Chan Eddie P
Vicary Keith
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