Interconnection network and crossbar switch for the same

Details Interconnection network and crossbar switch for the same Interconnection network and crossbar switch for the same

1994-02-28

1996-05-14

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG1, 364228, 3642292, 3642319, 3642294, 3642407, 36424296, 3642843, 3642844, G06F 1338, G06F 15173

Patent

active

055176194

ABSTRACT:
In a parallel computer including L=n.sub.1 .times.n.sub.2 .times. - - - .times.n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L.times.(1
.sub.1 +1
.sub.2 + - - - +1
.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N), 0.ltoreq.i.sub.1 .ltoreq.n.sub.1 -1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2 -1; - - - , 0.ltoreq.i.sub.N ; and .ltoreq.n.sub.N -1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L
.sub.k sets) of coordinates (i.sub.1, i.sub.2, - - - , i.sub.k-1, i.sub.k+1, - - - , i.sub.N) of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).

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