Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-09-20
2001-04-03
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S759000, C257S760000
Reexamination Certificate
active
06211569
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a structure of interconnection lines in integrated circuits and a method to fabricate the same, more specifically, to a structure of interconnection lines in integrated circuits for improving the thermal conductivity of metal lines therein and a method for fabricating the same.
BACKGROUND OF THE INVENTION
The fabricating of ultra-large-scale integrated (ULSI) circuits has a trend of shrinking the size of the circuits. The semiconductor devices that are fabricated on semiconductor substrates have more small size, the cost for manufacturing the devices is more lower. Thus, how to shrink the size of integrated circuits has become an important issue in the semiconductor process.
As the linewidth of integrated circuits is smaller than one-half micron meters or even smaller than one-quarter micron meters, the thermal conductivity of the intermetal dielectric layers in integrated circuits must be good enough for the reliability of the integrated circuits.
For the high-speed operation of the semiconductor devices on semiconductor substrate, the resistance-capacitance (RC) time delay value of the device must be small enough. Thus, a low dielectric-constant (k) material is preferred for interlayer dielectric layers or intermetal dielectric layers of integrated circuits to reduce the capacitance value of the integrated circuits for high-speed operation. Nevertheless, the low-k dielectric material is organic material and it has a poor thermal conductive ability for integrated circuits.
As the operation speed of integrated circuits is increased, the metal interconnection lines is heated. Thus, high-speed integrated circuits need good thermal-conductivity dielectric material as interlayer dielectric layers or intermetal dielectric layers of the integrated circuits for normal operation.
Referring to
FIG. 1
, it demonstrates a cross-section view of an integrated circuit formed on a substrate. A first metal pattern
130
is formed on an interlayer dielectric layer
110
and it communicates with the integrated circuit by metal plug
120
. Besides, a barrier layer
115
is formed between the metal plug
120
and the interlayer dielectric layer
110
for adhesion and forming an ohmic contact. Moreover, a second metal pattern
180
is formed on a cap layer
160
on an intermetal dielectric layer
150
and it connects to the first metal pattern
130
by using metal plugs
170
in the intermetal dielectric layer
150
. Furthermore, a barrier layer
165
is formed underneath the metal plugs
170
for adhesion.
The metal interconnection structure, which is shown in
FIG. 1
, is a conventional structure used in ULSI circuits. The thermal dissipation of the metal interconnection lines in the integrated circuits is implemented by dielectric layers between the metal interconnection lines and heat is conducted from a top metal pattern of the circuit to a first metal pattern
130
, finally, to the substrate
100
. If the dielectric layer in integrated circuits has no good thermal conductive ability, the thermal dissipation of the integrated circuits will be hardly reached.
According to the above discussion, normal organic low dielectric-constant material can not provide good thermal conductivity for integrated circuits. It is needed a metal interconnection structure of integrated circuits in order to enhance the thermal dissipation of integrated circuits during the normal operation of the circuits.
SUMMARY OF THE INVENTION
A structure of metal interconnection lines in integrated circuits for improving thermal conductivity of the metal interconnection lines, comprising: a substrate, wherein the integrated circuits formed on the substrate; an interlayer dielectric layer formed on the substrate; a silicon nitride layer formed on the interlayer dielectric layer; at least one first metal plug formed in the interlayer dielectric layer and the silicon nitride layer; a first metal pattern formed on the silicon nitride layer and communicated with the integrated circuits by the at least one first metal plug; a liner oxide layer formed on the first metal pattern and on the silicon nitride layer; an intermetal dielectric layer formed on the liner oxide layer; at least one second metal plug formed in the intermetal dielectric layer and the liner oxide layer; at least one silicon nitride plug formed in the intermetal dielectric layer and the liner oxide layer; a second metal pattern formed on the intermetal dielectric layer, the at least one silicon nitride plug and the at least one second metal plug, the second metal pattern communicated with the first metal pattern by the at least one second metal plug, wherein the at least one silicon nitride plug being adapted for improving thermal conductivity.
A structure of metal interconnection lines in integrated circuits for improving thermal conductivity of the metal interconnection lines, comprising: a substrate, wherein the integrated circuits formed on the substrate; a plurality of metal patterns formed on the substrate for interconnection lines of the integrated circuits, wherein the metal patterns isolated from each other by dielectric layers for insulating; at least one metal plug formed in one of the dielectric layers between one of the metal patterns and other of the metal patterns formed thereon, wherein the plurality of metal patterns communicating to each other and to the integrated circuits on the substrate by the at least one metal plug therebetween; at least one silicon nitride plug formed between one of the metal patterns and other of the metal patterns formed thereon, wherein the at least one silicon nitride plug adapted for improving thermal conductivity of the plurality of metal patterns.
REFERENCES:
patent: 6144099 (2000-11-01), Lopatin et al.
Baker & Botts L.L.P.
Crane Sara
Tran Thien F.
Worldwide Semiconductor Manufacturing Corp.
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