Fishing – trapping – and vermin destroying
Patent
1988-08-11
1991-08-20
Wojciechowicz, Edward J.
Fishing, trapping, and vermin destroying
357 55, 357 68, 437 67, 437180, H01L 2934, H01L 2144
Patent
active
050418980
ABSTRACT:
Trenches (2) are formed in three rows in a major surface of a semiconductor substrate (1). The major surface of the semiconductor substrate (1) including the inside of the trenches (2) is thermally oxidized. A first oxide film (4) filling the trenches is formed by thermal oxidation, a second oxide film (4) is formed in a region of the semiconductor substrate interposed between the trenches, and a third oxide film (3) is formed on the major surface of the semiconductor substrate excluding the region interposed between the trenches. The upper surfaces of the first, second and third oxide films (3, 4) are etched away to be flattened, whereby the semiconductor substrate (1) is exposed so that an interconnection (5) is formed on the remaining first and second oxide films (4).
REFERENCES:
patent: 4502913 (1985-03-01), Lechaton et al.
patent: 4819054 (1989-04-01), Kawaji et al.
patent: 4910575 (1990-03-01), Komeda et al.
S. D. Malaviya, "Deep Dielectric Isolation", IBM Technical Disclosure Bulletin, vol. 26, No. 7A (Dec. 1983), pp. 388-389.
K. P. Thiel et al., "Polymide Nitride Isolation", IBM Technical Disclosure Bulletin, vol. 27, No. 7B (Dec. 1984), pp. 4139-4140.
K. Yamabe and K. Imai, "Nonplanar Oxidation and Reduction of Oxide Leakage Currents at Silicon Corners by Rounding-Off Oxidation", IEEE Transactions on Electron Devices, vol. ED-34, No. 8 (Aug. 1987), pp. 1681-1687.
Tobita Yoichi
Urabe Takashi
Mitsubishi Denki & Kabushiki Kaisha
Wojciechowicz Edward J.
LandOfFree
Interconnection layer formed on embedded dielectric and method f does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interconnection layer formed on embedded dielectric and method f, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnection layer formed on embedded dielectric and method f will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1011934