Interconnection arrangements for testing microelectronic circuit

Details Interconnection arrangements for testing microelectronic circuit Interconnection arrangements for testing microelectronic circuit

1980-02-11

1981-10-13

Tolin, Gerald P.

Electricity: electrical systems and devices

Miscellaneous

361409, 324 73R, 29574, H01L 2700

Patent

active

042951828

ABSTRACT:
A wafer having microelectronic circuit chips thereon having electrical connections between the chips arranged so that effectively the chips are on a surface which at least in one direction is unbounded. The electrical connections may be arranged so that the chips are effectively on the surface of a cylinder, or they may be effectively on a helix. The electrical connections may optionally be arranged so that the chips are effectively on a toroid, or on an endless helix. The output connections from a chip adjacent one edge of the wafer may be connected through electrical conductors direct to the input connections of a chip adjacent the opposite edge of the wafer.

REFERENCES:
patent: 3302067 (1967-01-01), Jackson
patent: 3395318 (1968-07-01), Laemer
patent: 3605063 (1969-03-01), Stewart
patent: 3913072 (1975-10-01), Catt
patent: 4044453 (1977-08-01), Vorback
"Programmable Cellular Logic Arrays," R. G. Shoup, Thesis at Carnegie-Melon niversity, 1970 Computer Science, microfilmed by University Microfilms, Ann Arbor, Michigan, 1970.

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