Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
2007-07-17
2007-07-17
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C709S238000
Reexamination Certificate
active
11110344
ABSTRACT:
A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure includes routers in service or compute processor boards distributed in an array of cabinets connected in series on each board and to respective routers in neighboring row cabinet boards with the routers in series connection coupled to routers in series connection in respective neighboring column cabinet boards. The array can include disconnect cabinets or respective routers in all boards in each cabinet connected in a toroid. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.
REFERENCES:
patent: 5175865 (1992-12-01), Hillis
patent: 5546596 (1996-08-01), Geist
patent: 5841775 (1998-11-01), Huang
patent: 6680915 (2004-01-01), Park et al.
patent: 2005/0018665 (2005-01-01), Jordan et al.
patent: 2005/0193357 (2005-09-01), Honary et al.
Ron Brightwell and Lee Ann Fisk, “Scalable Parallel Application Launch on Cplant,”8 pp., Nov. 2001, Sandia National Laboratories, Albuquerque, NM.
Ron Brightwell, Lee Ann FISK, David S. Greenberg, Tramm Hudson, Mike Levenhagen, Arthur B. MacCabe, and Rolf Riesen, “Massively parallel computing using components” 29 pp. Parallel Computing 25 (2000) 243-266, Elsevier Science B.V.
Kevin Pedretti, Ron Brightwell and Joshua Williams, “Cplant Runtime System Supoprt for Multi-Processor and Heterogeneous Compute Nodes”, 8 pp., IEEE International Conference on Cluster Computer, Jun. 2002.
Timothy G. Mattson and Greg Henry, “An Overview of the Intel TFLOPS Supercomputer”, 12 pp., Intel Technology Journal vol. 2, No. 1, 1st Q, 1998.
Camp William J.
Tomkins James L.
Farber Madelynne J.
Kim Kenneth S.
Sandia Corporation
LandOfFree
Interconnection arrangement of routers of processor boards... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interconnection arrangement of routers of processor boards..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnection arrangement of routers of processor boards... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3812558