Interconnection area decision processor

Details Interconnection area decision processor Interconnection area decision processor

1987-02-10

1989-05-30

Lall, Parshotam S.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

048357057

ABSTRACT:
The present invention provides an interconnection area decision processor for deciding vertical widths of areas employed for interconnection of a gate array. The interconnection area decision processor predicts which interconnection area each signal net passes on the basis of previously created data on cell arrangement and data on arrangement of transistor rows on a chip to estimate interconnection congestion per channel on the basis of the result of prediction and decide the number of transistor rows to be assigned to each channel on the basis of the estimated interconnection congestion, thereby to create data on the vertical width of each channel. Thus, density of integration can be improved by increasing the number of tracks of channels having large numbers of interconnections and decreasing the number of tracks of channels having small numbers of interconnections.

REFERENCES:
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4613941 (1986-09-01), Smith et al.
"Automatic Placement and Routing of Gate Arrays", by Gary Robson, VLSI Design, Apr. 1984, pp. 35-43.
"An Over-Cell Gate Array Channel Router", by Howard E. Krohn, IEEE 20th Design Automation Conference, 1983, pp. 665-670.
"A Routing Program Applicable to Various Chip Structure of Gate Arrays", by Masaynki Terai et al., Joho Shori Gakkai, Ronbunshi, vol. 25, No. 3, May 1984, pp. 357-364.
Mayayuki Terai, Tomoyoshi Noda, Koji Sato and Toshihiko Yahara, "A Routing Program Applicable to Various Chip Structures of Gate Arrays", Johoshori Gakki Ronbunshi, vol. 25, No. 3 (1984).

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