Interconnect wiring with sidewalls and inter-wiring...

Details Interconnect wiring with sidewalls and inter-wiring... Interconnect wiring with sidewalls and inter-wiring...

1999-06-01

2001-11-20

Abraham, Fetsum (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S650000, C257S748000

Reexamination Certificate

active

06320264

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and method of manufacturing them, and more particularly to semiconductor devices and method of manufacturing them in which capacitance between wirings can be reduced, delamination of inter-wiring insulating films can be suppressed and complication of manufacturing process can be avoided.
BACKGROUND OF THE INVENTION
As semiconductor devices are integrated in a high density, and circuit patterns of the semiconductor devices become minute, spaces between wirings become narrow. As spaces between wirings become narrow, parasitic capacitance between adjacent wirings increases, so that operation speed of circuits becomes slower and power consumption of the circuits becomes large.
In order to effectively decrease the parasitic capacitance, a technique is proposed in which an insulating film disposed between wirings, such as an interlayer insulating film of a multi-layered wirings and the like, is formed by using material having low dielectric constant or permittivity. For example, in each of Japanese patent laid-open publication No. 3-97247, Japanese patent laid-open publication No. 8-115976 and Japanese patent laid-open publication No. 9-102492, a semiconductor device having multi-layered wiring structure as schematically shown in
FIG. 10
is disclosed.
In the conventional semiconductor device shown in
FIG. 10
, a first layer wiring
205
, a second layer wiring
206
and a third layer wiring
207
are provided on a semiconductor substrate
201
at three height regions
202
,
203
and
204
having different heights from the semiconductor substrate
201
, respectively. Among these wirings, for example, between the first layer wirings
205
, between the second layer wirings
206
and on each of these wirings
205
and
206
, there are provided interlayer insulating films
208
which comprise fluorine-containing silicon oxide (SiOF).
Also, as shown in
FIG. 11
in which like reference numerals designate identical or corresponding components, another prior art semiconductor device is proposed in which, instead of the above-mentioned interlayer insulating films
208
, insulating films
209
comprising Hydroxy Silsesquioxane are used in combination with, for example, plasma oxidation oxide films
210
. The Hydroxy Silsesquioxane is a kind of inorganic Spin On Glass (SOG) which has heat resistance of approximately 400 degrees Celsius and which has relative dielectric constant of approximately 3.0. In the structure of
FIG. 11
, wiring sidewall layers
212
comprising silicon oxide are formed on side wall portions of wiring layers
205
and
206
.
When, as shown in
FIG. 10
, the interlayer insulating films
208
are formed by using the fluorine-containing silicon oxide, however, it is necessary to make the content or concentration of fluorine in the interlayer insulating films
208
, for example, equal to or larger than 7 weight percent, in order to decrease the relative dielectric constant to, for example, 3.0 through 3.5 and thereby to decrease parasitic capacitance between wirings. However, when the interlayer insulating films
208
are formed by using the fluorine-containing silicon oxide which contains such a large amount of fluorine, delamination is prone to occur at the interface portion having large area, especially, for example, between the semiconductor substrate
201
, the plasma oxidation film
211
formed between the interlayer insulating films
208
, or the like and the interlayer insulating film
208
. Therefore, manufacturing yield of semiconductor devices deteriorates in this structure.
With respect to the semiconductor device shown in
FIG. 11
, the SOG film
209
made of inorganic material such as the Hydroxy Silsesquioxane and the like as used in this device has a relative dielectric constant higher than that of an insulating film of organic material. Therefore, in order to decrease the parasitic capacitance between wirings, it is required to further reduce the relative dielectric constant of this inorganic SOG film
209
. For this purpose, for example, in a thesis “Consideration of Materials for Porous Interlayer Insulating Film”, Proceedings of the 52th Symposium on Semiconductor and Integrated Circuits Technology, p. 62-67 (1997), Aoi, et al., a technique is proposed wherein silylating agent is applied to SOG solution to silylate it and the silylated SOG solution is treated with an amine. Thereby, relative dielectric constant is reduced to approximately 2.3, and also pore size can be reduced to obtain low hygroscopic characteristics. However, in this method, treatment of the SOG solution takes time and labor, and the SOG solution becomes unstable.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to improve the above-mentioned disadvantages of the prior arts.
It is another object of the present invention to decrease parasitic capacitance between wirings in a semiconductor device highly integrated and having minute patterns.
It is another object of the present invention to avoid delamination of insulating films between wirings in a semiconductor device highly integrated and having minute patterns.
It is another object of the present invention to decrease parasitic capacitance between wirings in a semiconductor device highly integrated and having minute patterns, without causing disadvantages such as complication of manufacturing process.
It is another object of the present invention to avoid delamination of insulating films between wirings in a semiconductor device highly integrated and having minute patterns, without causing disadvantages such as complication of manufacturing process.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a wiring in each of one or more wiring layers formed on a semiconductor substrate; and wiring sidewall layers which are formed on side edge portions of the wiring and which include fluorine-containing silicon oxide.
In this case, the one or more wiring layers may comprise a plurality of wiring layers which are respectively disposed in height regions having different heights from the semiconductor substrate.
Also, each of the wiring sidewall layers may have a double layer structure having an inner wall layer comprising silicon oxide and formed on the side edge portions of the wiring and an outer wall layer comprising fluorine-containing silicon oxide and formed on the outer surface of said inner wall layer.
It is also possible to form an inter-wiring insulating film comprising fluorine-containing silicon oxide on the outer surface of the wiring sidewall layers.
Further, it is possible to form thermally diffused regions of fluorine into which fluorine is thermally diffused from the wiring sidewall layers in the inter-wiring insulating layer and near the interfaces with the wiring sidewall layers.
It is further possible to form an inter-wiring insulating film comprising Hydroxy Silsesquioxane the outer surfaces of the wiring sidewall layers.
It is further possible to form thermally diffused regions of fluorine into which fluorine is thermally diffused from the wiring sidewall layers and in which said Hydroxy Silsesquioxane is dehydrogenated and density of the Hydroxy Silsesquioxane is lowered, in the inter-wiring insulating layer and near the interfaces with the wiring sidewall layers.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; forming a conductor layer for forming wirings in a wiring layer on the semiconductor substrate on which the insulating layer is formed; patterning the conductor layer for forming wirings to form wirings which are disposed in predetermined patterns; forming a film layer for forming wiring sidewall layers including fluorine-containing silicon oxide on the semiconductor substrate so as to cover the wirings; etching back the film layer for forming wiring sidewall layers

Affiliated with

Also associated with

Rating

Interconnect wiring with sidewalls and inter-wiring... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interconnect wiring with sidewalls and inter-wiring..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnect wiring with sidewalls and inter-wiring... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2580977