Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2006-09-13
2008-12-16
Williams, Alexander O (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257SE23145, C257SE23167, C257SE23161, C257SE23116, C257SE21579, C257S680000, C257S773000, C257S758000, C438S629000
Reexamination Certificate
active
07466027
ABSTRACT:
Interconnect structures are provided. An exemplary embodiment of an interconnect structure comprises a substrate with a low-k dielectric layer thereon. A via opening and a trench opening are formed in the low-k dielectric layer, wherein the trench opening is formed over the via opening and the via opening exposes a portion of the substrate. A liner layer is formed on sidewalls of the low-k dielectric layer exposed by the trench and via protions and a bottom surface exposed by the trench via portion, wherein the portion of the liner layer on sidewalls of the low-k dielectric layer exposed by the trench and via protions and the portion of the liner layer formed on a bottom surface exposed by the trench portion comprise different materials. A conformal conductive barrier layer is formed in the trench and via openings, covering the liner layer and the exposed portion of the substrate. A conductive layer is formed on the conductive barrier layer, filling in the trench and via openings.
REFERENCES:
patent: 6603204 (2003-08-01), Gates et al.
patent: 6677680 (2004-01-01), Gates et al.
patent: 6716742 (2004-04-01), Gates et al.
patent: 6831366 (2004-12-01), Gates et al.
patent: 6878615 (2005-04-01), Tsai et al.
patent: 6917108 (2005-07-01), Fitzsimmons et al.
patent: 2006/0027929 (2006-02-01), Cooney et al.
patent: 2006/0099802 (2006-05-01), Lin et al.
patent: 2006/0154464 (2006-07-01), Higashi
patent: 2006/0216932 (2006-09-01), Kumar et al.
patent: 2007/0032068 (2007-02-01), Ogawa
patent: 2007/0082132 (2007-04-01), Shinriki et al.
patent: 2007/0096321 (2007-05-01), Raaijmakers et al.
patent: 2007/0284746 (2007-12-01), Lopatin et al.
Chou Chia-Cheng
Ko Chung-Chi
Lin Keng-Chu
Taiwan Semiconductor Manufacturing Co. Ltd.
Thomas Kayden Horstemeyer & Risley
Williams Alexander O
LandOfFree
Interconnect structures with surfaces roughness improving... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interconnect structures with surfaces roughness improving..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnect structures with surfaces roughness improving... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4027160