Interconnect structures with engineered dielectrics with...

Details Interconnect structures with engineered dielectrics with... Interconnect structures with engineered dielectrics with...

2007-09-11

2007-09-11

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S758000, C257S760000, C257S701000, C257S211000

Reexamination Certificate

active

10683333

ABSTRACT:
A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

REFERENCES:
patent: 5869880 (1999-02-01), Grill et al.
patent: 6297150 (2001-10-01), Morinaga
patent: 6924240 (2005-08-01), Nobutoki et al.

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