Interconnect structures having patterned interfaces to minimize

Stock material or miscellaneous articles – Structurally defined web or sheet – Discontinuous or differential coating – impregnation or bond

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

428210, 428901, 428195, B32B 900

Patent

active

052523829

ABSTRACT:
Interconnect structures for integrated circuits and semiconductor chips are disclosed which employ patterned interfaces to minimize stress migration in the interconnects. The interfaces are patterned to have regions of substantially no adhesion and other regions of good adhesion. The regions of substantially no adhesion reduce stress migration in the interconnect, while the regions of good adhesion ensure adequate thermal contact, fabricability and mechanical integrity of the interconnect structures. The patterned interfaces can be formed either by treating the surfaces of the interconnect or adjacent insulator and passivation layers, or by forming patterned interlayers of material in the interfaces. Multiple layer interconnects can also be formed which incorporate similarly patterned interfaces.

REFERENCES:
patent: 4107726 (1978-08-01), Schilling
patent: 4424251 (1984-01-01), Sugishita et al.
patent: 4451326 (1984-05-01), Gwozdz
patent: 4508749 (1985-04-01), Brannon et al.
patent: 4725877 (1988-02-01), Brasen et al.
patent: 4774127 (1988-09-01), Reagan et al.
patent: 4782380 (1988-11-01), Shankar et al.
patent: 4786962 (1988-11-01), Koch
patent: 4824716 (1989-04-01), Yerman
patent: 4824803 (1989-04-01), Us et al.
patent: 4841354 (1989-06-01), Inaba
patent: 4881118 (1989-11-01), Niwayama et al.
patent: 4884120 (1989-11-01), Mochizuki et al.
Hey, H. P. W. et al., "Selective Tungsten on Aluminum for Improved VLSI Interconnects", IEDM 86, pp. 50-53, 1987.
Jackson, M. S. et al., "Stress Relaxation and Hillock Growth in Thin Films", Acta Metall., vol. 30, pp. 1993-2000, 1982.
Puttlitz, A. F. et al., "Semiconductor Interlevel Shorts Caused by Hillock Formation in Al-Cu Metallization", IEEE, vol. 12, No. 4, pp. 619-626, 1989.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Interconnect structures having patterned interfaces to minimize does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interconnect structures having patterned interfaces to minimize , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnect structures having patterned interfaces to minimize will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1903152

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.