Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-11-07
2004-02-24
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S751000, C257S758000, C257S762000
Reexamination Certificate
active
06696758
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to integrated circuit processing and, more particularly, to the introduction and patterning of interconnections on an integrated circuit.
2. Description of Related Art
Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send and/or receive signals external to the chip. Popular types of interconnections include aluminum alloy interconnections (lines) and copper interconnections (lines) coupled to individual devices, including other interconnections (lines) by interconnections through vias.
A typical method of forming an interconnection, particularly a copper interconnection, is a damascene process. A typical damascene process involves forming a via and an overlying trench in a dielectric to an underlying circuit device, such as a transistor or an interconnection. The via and trench are then lined with a barrier layer of a refractory material, such as titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The barrier layer serves, in one aspect, to inhibit the diffusion of the interconnection material that will subsequently be introduced in the via and trench into the dielectric. Next, a suitable seed material is deposited on the wall or walls of the via and trench. Suitable seed materials for the deposition of copper interconnection material include copper (Cu), nickel (Ni), and cobalt (Co). Next, interconnection material, such as copper, is introduced by electroplating or physical deposition in a sufficient amount to fill the via and trench and complete the interconnect structure. Once introduced, the interconnection structure may be planarized and a dielectric material (including an interlayer dielectric material) introduced over the interconnection structure to suitably isolate the structure.
Copper has become a popular choice of interconnection material for various reasons, including its low resistivity compared with the resistivity of aluminum or aluminum alloys. Nevertheless, copper interconnection material is not without its own limitations. One limitation is that copper does not adhere well to dielectric material. The barrier material on the side walls of a via and trench as explained above provides adhesion to the adjacent dielectric material. However, in the damascene process described above, no barrier material is present on the top of the interconnect material and, consequently, copper is typically in direct contact with the dielectric material. Poor adhesion of copper material to dielectric material contributes to electromigration by the copper material during, for example, current flow.
A second problem encountered by copper interconnection material involves the difficulty in completely filling a via with copper material. In a typical electroplating introduction process, voids can appear in the via. The voids tend to aggregate and create reliability issues for the interconnection. The voids also increase the resistance of the via.
Another limitation of copper interconnection material as it is currently introduced is the tendency of the formed interconnection to blister or form hillocks due to subsequent annealing steps typically encountered in the formation of integrated circuit devices at the wafer level. These blisters or hillocks disrupt the otherwise planarized layers of interconnections over the wafer.
What is needed are improved interconnect structures and techniques for improving the introduction and properties of an interconnection structure.
REFERENCES:
patent: 4574095 (1986-03-01), DeLuca et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4894260 (1990-01-01), Kumasaka et al.
patent: 4985750 (1991-01-01), Hoshino
patent: 5151168 (1992-09-01), Gilton et al.
patent: 5240497 (1993-08-01), Shacham et al.
patent: 5612254 (1997-03-01), Mu et al.
patent: 5695810 (1997-12-01), Dubin et al.
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5891513 (1999-04-01), Dubin et al.
patent: 6153935 (2000-11-01), Edelstein et al.
patent: 6169024 (2001-01-01), Hussein
patent: 6174812 (2001-01-01), Hsiung et al.
patent: 6197688 (2001-03-01), Simpson
patent: 6258707 (2001-07-01), Uzoh
patent: 6316359 (2001-11-01), Simpson
patent: 6350687 (2002-02-01), Avanzino et al.
patent: 6358832 (2002-03-01), Edelstein et al.
patent: 2001/0030366 (2001-10-01), Nakano et al.
patent: 1022770 (2000-07-01), None
patent: 62[1987]-270778 (1987-11-01), None
patent: 11288940 (1999-10-01), None
Brusic, “Copper Corrosion With and Without Inhibitors,” J. Electrochem. Soc., vol. 138, No. 8, pp. 2253-2258 (Aug. 1991).
Cho, et al., “Copper Interconnection with Tungsten Cladding for ULSI,” 1991 Symposium on VLSI Technology, pp. 39-40 (May 1991).
Cho, et al., “Electroless Cu for VLSI,” MRS Bulletin, pp. 31-38 (Jun. 1993).
Dubin, et al., “Selective Electroless Ni Deposition on a TiW Underlayer for Integrated Circuit Fabrication ,” Thin Solid Films, pp. 87-93 (1993).
Dubin, et al., “Selective and Blanket Electroless Cu Plating Initiated by Contact Displacement for Deep Submicron Via Contact Filling,” VMIC Conference, pp. 315-321 (Jun. 1995).
Gardner, et al., “Encapsulated Copper Interconnection Devices Using Sidewall Barriers,” VMIC Conference, pp. 99-108 (Jun. 1991).
Georgiou, et al., “Thick Selective Electroless-Plated Cobalt-Nickel Alloy Contacts to CoSi2, ” J. Electrochem. Soc., vol. 138, No. 7, pp. 2061-2069 (Jul. 1991).
Jagannathan, et al., “Electroless Plating of Copper at a Low pH Level,” J. Res. Develop., vol. 37, No. 2, pp. 117-123 (Mar. 1993).
Kiang, et al., “Pd/Si Plasma Immersion Ion Implantation for Selective Electroless Copper Plating on SiO2, ” Appl. Phys. Lett., vol. 60, No. 22, pp. 2767-2769.
Luther, et al., “Planar Copper-Polyimide Back End of the Line Interconnections for ULSI Devices,” VMIC Conference, pp. 15-21 (Jun. 1993).
Mak, “Electroless Copper Deposition on Metals and Metal Silicides,” MRS Bulletin, pp. 55-62 (Aug. 1994).
Murarka, et al., “Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing,” MRS Bulletin, pp. 45-51 (Jun. 1993).
Paunovic, et al., “Electrochemically Deposited Diffusion Barriers,” J. Electrochem. Soc., vol. 141, No. 7, pp. 1843-1850 (Jul. 1994).
Shacham-Diamond, “100 nm Wide Copper Lines Made by Selective Electroless Deposition,” J. Micromech. Microeng., pp. 66-72 (1991).
Shacham-Diamond, et al., “0.35 &mgr;m Cu-Filled Via Holes by Blanket Deposited Electroless Copper on Sputtered Seed Layer,” VMIC Conference, pp. 334-336, (Jun. 1995).
Sviridov, Electroless Metal Deposition from Aqueous Solution, Minsk Bielorussion State University, pp. 60-85 (1986).
Ting, et al., “Selective Electroless Metal Deposition for Integrated Circuit Fabrication,” J. Electrochem. Soc., vol. 136, No. 2, pp. 456-465 (Feb. 1989).Feb. 14, 2003.
Ueno, et al., “A Half-Micron Pitch Cu Interconnection Technology,” 1995 Symposium on VLSI Technology, pp. 27-28 (1995).
Wang, “Barriers Against Copper Diffusion into Silicon and Drift Through Silicon Dioxide,” MRS Bulletin, pp. 30-40 (Aug 1994).
Wong, et al., “Electroless Copper Deposition for Multilevel Matallization,” Mat. Res. Soc. Symp. Proc., vol. 203, pp. 347-356 (1991).
Hymes, et al., “Passivation of Copper by Silicide Formation in Dilute Silane,” Conference Proceedings ULSI-Vll, Materials Research Society, pp. 425-431 (1992).
Lopatin, S.D., et al., “Thin Electroless Barrier for Copper Films,” Proceedings of the SPIE, vol. 3508, Bellingham, VA, Sep. 23, 1998, pp. 65-77.
Sambucetti, C.J., et al., “Electroless Deposition of Thin Alloys Layers for Metal Passivation and Solder Barriers,” Electrochemical Society Proceedings, Pennington, NJ, Aug. 31, 1997, pp. 336-345.
Datta Madhav
Dubin Valery M.
McGregor Paul
Thomas Christopher D.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Tuan H.
LandOfFree
Interconnect structures and a method of electroless... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interconnect structures and a method of electroless..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnect structures and a method of electroless... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3323207