Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-11-22
2003-01-14
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C174S263000, C361S803000
Reexamination Certificate
active
06506981
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to electronic interconnect structures, and in particular to interconnect stacks with fuse or anti-fuse links defined between profiled holes.
BACKGROUND OF THE INVENTION
Electronic interconnect structures are known in the art. In their simplest form, these interconnect structures are embodied by printed circuit boards (PCBs) or printed wiring boards (PWBs). These types of boards use conductive traces or wire conductors to transmit electronic signals. One common application of PCBs and PWBs is in routing signals to and from electronic circuits and integrated circuits (ICs) in particular. In traditional PCBs the traces are provided in one or two planes; the top and bottom surfaces of the PCB. The number of traces which can be printed on a surface is limited by factors such as signal cross talk, current density and ohmic heating. Hence, traditional PCBs can only support a few hundred interconnections in PCBs of modest size and packing density.
More recently, multi-layered printed circuit boards (PCBs) have been employed to extend the number of interconnects by using several planes of traces. The planes are separated by dielectrics. Electrical connections between the planes are usually provided by vertical metal pillars or conductive vias.
Further information about multi-layered PCBs can be found in U.S. Pat. No. 4,498,122 entitled “High-Speed, High Pin-Out LSI Chip Package” and other open literature.
Multichip modules (MCMs) are packages with high density substrates (finer than 100 &mgr;m lines and spaces) and bare die (usually more than five). MCM is the current method used to interconnect multiple dice without adding substantial overhead in terms of volume and reliability.
The prior art also teaches more advanced interconnect structures in which interconnections can be programmed by establishing or breaking electrical connections. For example, U.S. Pat. No. 4,888,665 entitled “Customizable Circuitry”, discloses interconnect circuits using orthogonally extending multi-wire layers adjacent ones of which can be fused and anti-fused as necessary to program interconnect nodes. Further teachings on multi-layered interconnect structures can be found in U.S. Pat. No. 4,899,439 entitled “Method of Fabricating a High Density Electrical Interconnect”; U.S. Pat. No. 5,264,664 entitled “Programmable Chip to Circuit Board Connector”.
Multi-layered interconnect structures have also been used in flexible electrical wiring cables, as taught by U.S. Pat. No. 5,373,109 entitled “Electrical Cable Having Flat, Flexible, Multiple Conductor Sections”. It has also been recognized that it may be desirable, in certain applications to enhance component density by laterally stacking vertically oriented die or die-support substrates and providing for an edge connect. For information on such laterally stacked structures the reader is referred to U.S. Pat. Nos. 5,266,833; 4,983,533 and 4,764,846. Furthermore, it has been recognized that it may be desirable, in certain applications, to vertically stack horizontally-disposed dice in two or more layers. The reader is referred to U.S. Pat. Nos. 5,481,134; 5,481,133; 5,468,997; 5,455,445; 5,434,745 and 5,128,831 for a review of these teachings.
In U.S. Pat. Nos. 5,623,160 and 5,691,209 the present inventor discloses a signal-routing or interconnect substrate, structure and apparatus. The lattice is preferably formed in a plural-layer structure, whereby each required interconnect signal has one or more dedicated layers of a planar, thin-film conductor that is coextensive with the substrate. An array of vertical pillars or conductive vias is provided in the substrate, each pillar effectively providing an inner conductor either electrically connected with a conductive layer or electrically insulated therefrom by an insulative region. The pillars can be selectively connected or disconnected from the conductive layers by fusing and anti-fusing techniques.
Increasing density of ICs, whose linewidths (i.e., widths of conductive traces and pins) are constantly shrinking, have made current density a major concern in dense interconnect structures. Corresponding improvements to interconnect structures are documented in U.S. Pat. No. 5,969,321 to Smooha, who teaches how to avoid current crowding in a multi-layered interconnect structure by using two sets of separated vias. As well as in U.S. Pat. No. 5,973,396 to Farnworth who discloses an interconnect structure or die in which there can be vertical and horizontal fuse elements. Farnworth's die permits one to decrease the die size or shrink the die stack.
Continuing increases in IC densities and reductions in die real estate demand further down-scaling and improvements to interconnect structures. Applications of interconnect stacks in fields other than pin-out of ICs place additional demands. For example, interconnect stacks have been proposed for use in memories. For further information the reader is referred to “Laminated Memory: A New 3-Dimensional Packaging Technology for MCMs”, proceedings of 1994 IEEE, Multichip Module Conference, pp. 58-63.
Several prior art approaches have focused on antifuse structures and materials. For example, U.S. Pat. No. 5,789,764 to McCollum teaches an antifuse material having a thickness designed to impart a desired target programming voltage to the antifuse. The antifuse can be used in via antifuses or stacked antifuses. Additional teaching on antifuse structures can be found in Chiang, “Antifuse Structure Comparison for Field Programmable Gate Arrays”, IEEE, IEDM, 1992, pp. 611-614; Cohen, “A Flat-Aluminum Based Voltage-Programmable Link for Field-Programmable Devices”, IEEE Translations on Electronic Devices, vol. 41, No. 5, May 1994, pp. 721-724; Hu, “Interconnect Devices for Field Programmable Gate Array”, 1992, IEEE, IEDM, pp. 591-594; and Pauleau, “Interconnect Materials for VLSI Circuits”, Solid State Technology, vol. 30, April 1987, pp. 155-162.
As a result of the advances made with wafer fabrication, today's semiconductor chips are smaller, run at a higher frequency, generate more heat and require more interconnections due to increased complexity. The rapid increase in input/output (I/O) and space limitation requirements of new packaging place difficult demands on the interconnect density and electrical performance of package substrates. In chip-scale, area-array methods, a small form factor is needed, and there is no mechanism to accommodate the transition from the chip's I/O density to the board's density. Silicon shrinkage, advances in design tools, system architecture and package assembly have all driven higher densities. Bump pitch decreases for high-I/O-count packaging and shorter development cycles are pushing substrate suppliers to meet the new requirements.
Because packaging interconnect technology has not kept pace with the developments of the fabrication process and chip design, the current techniques for package interconnections are expensive and therefore prohibitive to mainstream applications. Presently, interconnection technology, or the lack thereof, is viewed as the major bottleneck in creating new electronic devices with higher performance, faster time-to-market, and lower costs.
Despite the various teachings related to MCM structures, further down-scaling remains a difficult task. It would be an advance in the art to provide an interconnect structure with fuse or antifuse type links which are more sensitive and permit further down-scaling of the interconnect structure. Specifically, it would be an advance in the art to develop more accurately and precisely controllable fuse and anti-fuse links in such interconnect structures.
OBJECTS AND ADVANTAGES OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an interconnect structure in the form of an interconnect stack having more precisely controlled fuse and/or anti-fuse links. In particular, it is an object of the invention to provide fuse and anti-fuse links which more accurately and precisely define the l
Lumen Intellectual Property Services Inc.
Paladini Albert W.
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