Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2001-01-17
2002-12-31
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S723000, C257S737000, C257S778000
Reexamination Certificate
active
06501174
ABSTRACT:
FIELD OF INVENTION
This invention is directed to the field of semiconductor assembly packaging generally and the attachment of individual chips to multichip products specifically.
BACKGROUND OF THE INVENTION
Those in the semiconductor industry face a never ending effort to increase productivity and decrease the size of computer products. As the size of overall packages decreases so does the size of the individual chips that form the overall package. Conversely, the efficiency and power of the overall packages increase with each generation. Each generation faces different challenges introduced by shrinking size and changing processes.
Currently one of the challenges exists on the chip interconnect level. Individual chips must be connected to each other and/or top surface electrical components, like resistors and capacitors. As the overall individual chip size decreases, so does the size of the interconnecting components. Individual chips on an overall package are usually connected the overall package by means of a solder connection. The solder connections, usually solder bumps correspond to interconnect structures on the package.
The amount of solder in a C4 (control collapsed chip connection) or solder bump forming each discrete solder bump must correspond to the pitch of the chip and also to the corresponding interconnect structure pad. There must be sufficient amounts of solder present to ensure electrical connection of an individual chip and long term reliability. As the size of the individual chip decreases so does the total area of the chip available for interconnecting in general and the area of an individual solder bump specifically. As a consequence, the chance of solder bleed out increases as solder bump size decreases.
Solder bleed out occurs where there is solder wetting in a location other than the desired location of the solder fillet. That is, the solder intended to create an electrical connection is misdirected due to the influence of other factors. One of the ways that solder bleeding can occur is where the solder can wet and spread onto a line connected to a C4 pad during chip joining causing low solder volume in the C4 joint. Low solder volume can cause reliability problems.
Current technology solder C4s can comprise low melting point lead/tin alloys. An example of a low melting point solder is a 37/63 eutectic solder. A typical corresponding structure pad can comprise copper or a copper alloy and is plated. Common plating materials or combinations of materials include nickel, phospate and gold. The most common material to bleed out is gold. Where gold bleed out is a problem some semiconductor designers have reengineered the shape of the pads to minimize the amount of gold necessary to ensure electrical connection. Other designers have tried other approaches including solder dams and laser ablation.
Thus there remains a need for an interconnect method that minimizes the risk of solder bleedout, ensures electrical connection and is reliable.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an interconnect mechanism that minimizes the risk of solder bleed out.
It is also an object of the instant invention to provide an interconnect structure that maintains electrical integrity.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to A semiconductor interconnecting mechanism, comprising:
An interconnect structure having a top surface and a body, the top surface containing at least one discrete structure capable of electrically communicating with an discrete object;
At least one top surface electrical metallurgy disposed on the top surface of the interconnect structure, wherein said top surface electrical metallurgy is not in physical contact with any of the at least one discrete structures;
An interconnect spacer, having a line portion and two via portions, the line portion having two ends and each of the via portions having two ends, wherein the line portion is disposed within the body of the interconnect structure and wherein one of each of the via portion ends is in physical contact with one of the ends of the line portion, and wherein one of the two via ends not in contact with the line portion is in physical contact with one of the electrical metallurgy and the other of the two via ends not in contact with the line portion is in electrical communication with one of the at least one discrete structures.
REFERENCES:
patent: 5468997 (1995-11-01), Imai et al.
patent: 5652466 (1997-07-01), Hirakawa et al.
patent: 4-62961 (1992-02-01), None
Pillai Edward R.
Rapp Linda L.
Semkow Krystyna W.
International Business Machines - Corporation
Thomas Tom
Townsend Tiffany L.
Vu Hung Kim
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