Interconnect structure for FPGA using a multiplexer

Details Interconnect structure for FPGA using a multiplexer Interconnect structure for FPGA using a multiplexer

1998-02-13

1999-08-17

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

327 99, H03K 17693

Patent

active

059399309

ABSTRACT:
A six-input multiplexer is disclosed using only two transistors in the signal path from an input port to the output port. The multiplexer uses control signals that are not decoded. The multiplexer uses three control signals and requires that the control signal combinations 000 and 111 not be used. The other six control signal combinations 001, 010, 011, 100, 101, and 110 can be used to select between six input signals by placing only two transistors in the signal path, taking advantage of the fact that two of the three control signals are the same and the third is different from the other two. A compact layout results when two multiplexers use common input signals. According to another aspect of the invention, an interconnect structure is provided that includes two multiplexers, each multiplexer receiving an input signal from a buffered output of the other multiplexer.

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