Interconnect structure for electronic devices

Details Interconnect structure for electronic devices Interconnect structure for electronic devices

2002-02-01

2004-02-17

Wong, Don (Department: 2821)

Electric lamp and discharge devices: systems

Plural power supplies

Plural cathode and/or anode load device

C257S668000

Reexamination Certificate

active

06693384

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to interconnect structures for electronic devices, and more particularly, in certain embodiments, to display devices such as flat panel displays.
BACKGROUND OF THE INVENTION
While the present invention has many aspects and embodiments, this section will focus on those aspects which relate to display devices. While there are a large number of various different types of display devices, one very common display device utilizes pixel electrodes to control a display medium such as a liquid crystal display (LCD) layer in order to create an image. These pixel electrodes may control other types of display media such as electrophoretic display media, organic light emitting diodes (OLED), or a polymer light emitting diode (PLED). Typically, a pixel electrode works by creating locally an electric field relative to another electrode. A display medium is sandwiched between the two electrodes and reacts to this electric field. Well known examples of such types of displays are the active matrix liquid crystal displays used in modern laptop computers and passive matrix display used in modem PDA computers or cellular phones.
FIG. 1
illustrates an example of a backplane for an active matrix display in the prior art. As is well known, a plurality of pixel electrodes, such as pixel electrode
9
C, are arranged in an array of rows and columns. Each row of pixel electrodes is controlled by a row electrode such as row electrodes
2
,
3
, and
4
. At least one transistor device is coupled to each pixel electrode in order to control the updating of new data to the pixel electrode in order to change the image being displayed. For example, as shown in
FIG. 1
, the field effect transistor (FET)
9
A couples the pixel electrode
9
C to the data line
1
on column
5
when row
2
receives a high voltage signal (e.g. 5 volts), causing the data value provided on column
5
to be stored onto the capacitor
9
B which in turn causes the storage of a voltage value on the pixel electrode
9
C. As is known in the art, each row receives a plurality of data in parallel substantially simultaneously as each row's signal line goes high, causing the gate electrode to allow the transistor device to conduct, thereby causing the data from the associated column to be written to the pixel electrode through the capacitor. It will be appreciated in certain embodiments that the capacitor is merely optional and the capacitance of the FET device itself will be sufficient to store the charge for the pixel electrode to thereby maintain the pixel electrode at a certain voltage. Thus the display is updated one row at a time where each row receives in parallel a plurality of data from the parallel columns, such as columns
5
,
6
,
7
and column
8
as shown in FIG.
1
. It will be appreciated that each pixel cell includes a display driver such as display drivers
9
,
10
, and
11
which control associated pixel electrodes in the display shown in FIG.
1
.
FIG. 2
illustrates an example of a conventional passive matrix display. A passive matrix display is similar to the active matrix display except that each row and column is controlled by one driver attached to that row or column. A conventional passive matrix
100
is a liquid crystal display passive matrix comprising a number of layers. The display comprises a top substrate
102
and a bottom substrate
103
. The top substrate
102
and the bottom substrate
103
can be made out of glass. Each of the top substrate
102
and the bottom substrate
103
is coated with a plurality of transparent conductive lines arranged in an array of rows
104
or column
106
. The rows
104
and the columns
106
are made out of a highly transparent material, typically, indium tin oxide (ITO) to prevent the conductors from interfering with the image quality. As well understood, the rows and columns of the transparent conductors operate as a grid of row and column of pixel electrodes, which passes the current needed to activate the screen elements and control the pixels on the display screen. On top of each of the transparent conductors, an alignment layer
108
may be deposited. The alignment layer is typically a polymer material that has a series of parallel grooves running across it to help align the liquid crystal molecules in the appropriate direction, and to provide a base on which the molecules are attached. Spacer beads
110
may also be disposed between the two alignment layers
108
. The spacer beads
110
help maintain a uniform distance between the two substrates
102
and
103
when they are placed together.
The edges are then sealed with an epoxy, but with a gap left in one corner. The corner allows liquid-crystal materials
111
to be injected between the sheets (in a vacuum) before the plates are sealed completely. Next, polarizing layers
112
, which are linear light filters, are applied to the outer-most surfaces of each of the substrate
102
and
103
. The polarizing layer
112
are arranged to match the orientation of the alignment layers
108
. A backlight (not shown) can also be added, typically in the form of cold-cathode fluorescent tubes mounted along the top and bottom edges of the panel, the light from these being distributed across the panel using a plastic light guide or prism.
FIG. 3
illustrates the passive display
100
driven by a row driver
114
and a column driver
116
. This figure shows that an image
120
is formed when the row driver
114
and the column drive
117
passes signals along the corresponding row
106
and column
104
of the display
100
. The column driver
116
and the row driver
114
are typically integrated circuits containing input/output circuit elements that are customarily fabricated upon semiconductor (silicon) chips to drive the display
100
. The integrated circuits typically include the transistor, resistor and capacitor elements required to perform the circuit function (e.g., diving the display). The column driver
116
and the row driver
114
can be integrated into the substrate of the display, e.g, chip-on-glass (COG), or fabricated on a package that is attached to the display, e.g., chip-on-flex (COF) or tape automated bonded (TAB).
While the foregoing display architecture works well generally for many types of applications, it is well known that manufacturing these displays is expensive due to poor yields especially when the size of the display is large. It is also well known that to save cost, the silicon used to make the display drivers (e.g., drivers for a passive matrix display), are fabricated to be as small as possible. One problem with this cost saving approach is that the driver interconnections to the display become extremely complex and unreliable which, further hinders high yield.
FIG. 4
illustrates that a substrate of the display
100
has a pitch P
3
wherein the pitch is defined as the distance between two adjacent lines of display conductors (e.g., the distance between conductor row
104
and conductor row
105
). Usually, lines of conductor have a certain width, then the pitch is defined by the distance between the middle of one line to the middle of the other line. A carrier
120
including the driver chip
114
is shown to connect to the display
100
. The driver
114
is fabricated from a small piece of silicon to minimize the cost of the display. Because of the size reduction, the IC driver
114
has a pad pitch P
1
that is substantially smaller than the pitch P
3
, (a pad pitch on an IC is defined as the distance between the middle of a pad and the middle of an adjacent pad). Pitch P
2
, which is the interconnection pitch directly at the edge of the carrier
120
to the display, may be as large as the pitch P
3
. However, the complex interconnection leads from the driver
114
to the carrier
120
still remains the problem. This leads to poor yield problems. For example, though not shown in
FIG. 4
, in actuality, the routing is much more complex, especially when the display's arrays of conductors comprise many more conductors. For examp

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