Interconnect structure encased with high and low k...

Details Interconnect structure encased with high and low k... Interconnect structure encased with high and low k...

2005-05-09

2008-08-12

Thai, Luan (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S775000, C257S776000, C257SE21575, C257SE21597, C438S667000, C438S672000, C438S216000, C438S287000

Reexamination Certificate

active

07411305

ABSTRACT:
A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k material placed adjacent to at least one surface of the interconnect and extending over the thermal diffusion distance of the interconnect. The high-k material improves the critical current density of the interconnect by increasing the heat capacity and thermal conductivity of the interconnect. The high-k material can be placed on the sides, top and/or bottom of the interconnect. In multiple wire interconnects, the high-k material is placed between the wires of the interconnect. A low-k material is placed beyond the high-k material to reduce the capacitance of the interconnect. The combination of low-k and high-k materials provides an interconnect structure with improved ESD robustness and low capacitance that is well suited for an ESD device. The interconnect to the receiver, which does not carry a high current, is surrounded by a low-k material for reduced capacitance and performance advantages.

REFERENCES:
patent: 5514892 (1996-05-01), Countryman et al.
patent: 5744865 (1998-04-01), Jeng et al.
patent: 5821621 (1998-10-01), Jeng
patent: 7052990 (2006-05-01), Kim
patent: 2006/0134836 (2006-06-01), Knapp et al.

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