Interconnect structure and method to achieve unlanded vias for l

Details Interconnect structure and method to achieve unlanded vias for l Interconnect structure and method to achieve unlanded vias for l

1997-03-31

1999-08-10

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

216 18, 216 38, 216 39, 257774, 438637, 438672, 438723, 438737, H01L 2100

Patent

active

059358688

ABSTRACT:
A method of forming an interconnect structure using a low dielectric constant material as an intralayer dielectric is described. In one embodiment, the present inventive method comprises the following steps. A conductive structure that is surrounded by a low dielectric constant material on its side surfaces is formed. A first inorganic insulator is formed over at least a portion of the low dielectric constant material. A second inorganic insulator is formed over the first inorganic insulator. A photoresist layer is deposited and then patterned to form an unlanded via in the second inorganic insulator. The second inorganic insulator and a portion of the first inorganic insulator are etched in order to form the unlanded via.

REFERENCES:
patent: 5274912 (1994-01-01), Olenick et al.
patent: 5677239 (1997-10-01), Isobe
patent: 5741626 (1998-04-01), Jain et al.
patent: 5776834 (1998-07-01), Avanzino et al.

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