Interconnect structure and method of forming

Details Interconnect structure and method of forming Interconnect structure and method of forming

1996-02-29

1998-09-15

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257760, H01L 2348, H01L 2352, H01L 2940

Patent

active

058083626

ABSTRACT:
A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).

REFERENCES:
patent: 4974056 (1990-11-01), Brodsky et al.
patent: 5108945 (1992-04-01), Matthews
patent: 5243220 (1993-09-01), Shibata et al.
patent: 5262655 (1993-11-01), Ashida
patent: 5369303 (1994-11-01), Wei
patent: 5612557 (1997-03-01), Hondo et al.
patent: 5633522 (1997-05-01), Dorleans et al.
patent: 5670794 (1997-09-01), Manning
patent: 5708303 (1998-01-01), Jeng

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