Interconnect structure and method for fabricating the same

Details Interconnect structure and method for fabricating the same Interconnect structure and method for fabricating the same

2006-01-31

2006-01-31

Ghyka, Alexander (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S774000

Reexamination Certificate

active

06992393

ABSTRACT:
A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

REFERENCES:
patent: 6376394 (2002-04-01), Tsai et al.
patent: 6661097 (2003-12-01), Clevenger et al.
patent: 6774489 (2004-08-01), Russell et al.
patent: 6806579 (2004-10-01), Cowley et al.
patent: 2004/0058526 (2004-03-01), Cowley et al.
patent: 2004/0152295 (2004-08-01), Cooney et al.
patent: 2004/0262764 (2004-12-01), Gambino et al.

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