Interconnect structure

Details Interconnect structure Interconnect structure

2001-02-21

2003-04-29

Paladini, Albert W. (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S255000, C174S261000, C174S262000, C174S264000, C361S760000, C361S767000, C361S779000, C361S803000, C257S778000

Reexamination Certificate

active

06555759

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention pertains to the field of forming interconnects and, in particular, to the field of wafer packaging.
BACKGROUND OF THE INVENTION
Prior art conventional Direct Flip Chip (“DFC”) packaging technology and Chip Scale Package (“CSP”) packaging technology provide integrated circuit (“IC”) assemblies that address Original Equipment Manufacturer (“OEM”) requirements for smaller, thinner, lighter, denser, and lower cost packages for ICs. However, reliability and cost of these prior art, conventional packaging technologies continue to be important issues. A brief outline of the above-identified prior art conventional packaging technologies and the problems they face follows with reference to
FIGS. 1 and 2
.
In particular,
FIG. 1
shows, in pictorial form, underfilled Flip Chip Assembly
100
that is fabricated in accordance with prior art DFC packaging technology. As shown in
FIG. 1
, wafer die
110
(having a coefficient of thermal expansion (“CTE”) of about 3 ppm/° C.) is bonded to interconnect joints
120
1
-
120
5
and interconnect joints
120
1
-
120
5
are bonded, in turn, to (mounted on) printed circuit board (“PCB”)
140
(having a CTE of about 14 to 21 ppm/° C.). In addition, underfill material
130
is disposed between wafer die
110
and PCB
140
to surround interconnect joints
120
1
-
120
5
. Thermal mismatch between the various package materials (for example, CTE differences between wafer die
110
and PCB
140
) causes high residual stresses, resulting in device failure at connections between vias and interconnect joints
120
1
-
120
5
and at connections between PCB
140
and interconnect joints
120
1
-
120
5
. In accordance with this prior art packaging technology, stress is reduced, and reliability is thereby enhanced, by surrounding interconnect joints
120
1
-
120
5
with underfill material
130
(for example, a thermo-set polymer). However this prior art method of stress reduction does not reduce device-to-board interfacial stresses (i.e., stresses between wafer die
110
and PCB
140
), instead, it redistributes them into a greater area to reduce stress and strain at interconnect joints
120
1
-
120
5
. Unfortunately, this prior art method of stress reduction has the following drawbacks: (a) inherent processing problems with underfill material
130
relating to dispensing/injection and (b) the fact that, after underfill material
130
is cured, encapsulated interconnect joints
120
1
-
120
5
cannot be reworked in case of failure. The fact that encapsulated interconnect joints
120
1
-
120
5
cannot be reworked in case of failure drives a need to have a “Known Good Die” (“KGD”) before surface mounting it to PCB
140
. This can be very costly for assembly manufacturers.
Lastly, the above-identified problems necessitate that an interposer (flexible or rigid) of some kind be used in addition to the DFC packing technology. Unfortunately, this adds to the size and cost of the package, while decreasing device functional performance.
Flip Chip Technologies, Inc. of Phoenix, Ariz. has adopted an Ultra Chip Scale Package (“CSP”) packing technology to enhance the strength of interconnect joints either by increased joint geometry (height) or by utilizing new, and more expensive, solder joint alloys having greater mechanical strength. The purpose is to increase the life expectancy of the device at the solder interconnect joints. However, underfill material is still needed in the package assembly so that solder interconnect joints pass more than 200 thermal cycles (−40° C. to 125° C.) when larger die size is required. See an article by D. S. Patterson, P. Elenius, and J. A. Leal entitled “Wafer Bumping Technologies—A Comparative Analysis of Solder Deposition Processes and Assembly Considerations,
EEP—
Vol. 19-1,
Advances in Electronic Packaging—
1997 Volume 1
ASME
1997, pp. 337-351.
FIG. 2
shows, in pictorial form, &mgr;BGA® CSP Assembly
200
that is fabricated in accordance with prior art &mgr;BGA® CSP packaging technology of Tessera Inc. of San Jose, Calif. (“Tessera”). As shown in
FIG. 2
, wafer die
210
(having a CTE of about 3 ppm/° C.) is encapsulated in compliant elastomer layer
220
. In accordance with this packaging technology, compliant elastomer layer
220
is supposed to provide a decoupling mechanism between wafer die
210
and PCB
250
. As further shown in
FIG. 2
, compliant elastomer layer
220
is bonded to interposer
230
, and interposer
230
is bonded, in turn, to interconnect joints
240
1
-
240
5
. As still further shown in
FIG. 2
, interconnect joints
240
1
-
240
5
are bonded to PCB
250
(having a CTE of about 14 to 21 ppm/° C.). In addition, first level interconnects
225
and
226
are highly compliant leads that are formed in an “S” shape.
Although this prior art packaging technology allows wafer die
210
to move independently of PCB
250
, it significantly reduces device reliability because of the high CTE of compliant elastomer layer
220
, i.e., the bonded leads are forced into excessive deflection by compliant elastomer layer
220
. As shown in
FIG. 2
, Tessera's solution to this problem was to construct highly compliant leads (“S” shaped first level interconnects
225
and
226
) to take up these large strains. Unfortunately, this prior art packaging technology has tight process windows, which results in low assembly yields, higher costs, and low first level interconnect reliability.
In addition, the prior art CSP packaging technology requires the use of interposer
230
(for example, Flex or TAB tape) which adds to the cost of the package and reduces assembly yields. In further addition, the prior art CSP packaging technology requires customized equipment for high volume manufacturing, which customized equipment can be very costly.
As one can readily appreciate from the above, a need exists in the art for a method for wafer level IC packaging that: (a) can eliminate underfill layers; (b) enables rework to be done at board and chip level assembly; (c) minimizes the effects of thermal mismatches between PCBs and chip assemblies in a cost effective manner; (d) enables testing at the wafer level; and (e) can eliminate the need for an interposer.
SUMMARY OF THE INVENTION
Embodiments of the present invention advantageously satisfy the above-identified need in the art and provide a method for forming interconnects that can be applied to provide wafer level IC packaging. In accordance with the present invention, one can provide wafer level IC packaging that: (a) can eliminate underfill layers, thereby enhancing packaging reliability; (b) enables rework to be done at board and chip level assembly; (c) minimizes the effects of thermal mismatches between printed circuit boards(“PCBs”) and chip assemblies in a cost effective manner; (d) enables testing at the wafer level; (e) can eliminate the need for an interposer, thereby reducing material and processing cost; and (f) can be fully integrated into existing semiconductor manufacturing lines. Further embodiments of the present invention: (a) enable high density of packaging at the wafer level by enabling the size of interconnect joints to be minimized without reducing their mechanical integrity; (b) provide a chip size, high density, high power package with an integral, low profile, fin heat sink on the backside of the wafer; (c) eliminate solder paste printing, solder ball mounting, and flux cleaning by forming contact metallurgy using wet or dry processing methods such as, for example and without limitation, physical vapor deposition and high deposition rate electroplating of various metal alloys; and (d) depending on the outer joints, reduce device damage from alpha particles emitted by lead-containing solder interconnects.
An embodiment of the present invention is a method for forming interconnects that comprises: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer. A further embodiment of the present invention comprise

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