Interconnect structure

Details Interconnect structure Interconnect structure

1999-05-25

2002-04-02

Wong, Don (Department: 2821)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C029S592000

Reexamination Certificate

active

06365967

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of semiconductor devices and structures for testing unpackaged semiconductor devices having raised or bumped bond pads.
More particularly, the invention relates to an interconnect structure having a conductive pillar and alignment grid for contacting the bumps, balls, or bonding pads of a semiconductor device being tested.
2. Description of the Related Art
Many semiconductor devices are supplied by semiconductor manufacturers as flip chip devices or bumped chip scale packages for use in memory modules. In general, ball grid array (BGA) packages were developed to meet the demand for integrated circuit packages having higher lead counts and smaller footprints. A BGA package is typically a square package with terminals, normally in the form of an array of solder balls, protruding from the bottom of the package. These terminals are designed to be mounted onto a plurality of bonding sites located on the surface of a printed circuit board (PCB) or other suitable substrate. For some applications, solder bumps are deposited directly onto the surface of an IC itself and used for attachment to the PCB (commonly referred to as direct chip attach or flip chip).
Semiconductor die using BGA or an other raised topology are referred to as “bumped” die. Bumped semiconductor die include bond pads formed with a bump or ball of solderable material such as a lead-tin alloy. Bumped dice are often used for flip chip bonding wherein the die is mounted face down on a substrate, such as a printed circuit board, and then attached to the substrate by welding or soldering. Typically the bumps are formed as balls of material that are circular in a cross sectional plane parallel to the face of the die. The bumps typically have a diameter of from 0.15 mm to 2 mm.
A particular type of flip chip implementation is referred to as a chip scale package, because the total package size is similar or not much larger than the size of the die itself. In a chip scale package, the solder ball terminals are typically disposed underneath the semiconductor die to reduce the package size.
Various testing systems have been developed for testing BGA type packages, such as chip scale packages. These systems typically include a temporary carrier suitable for holding the package. In the temporary carrier, a non-permanent electrical connection is made between contact locations on the die (e.g., balls or bumps) and external test circuitry associated with the test apparatus. The balls provide a connection point for testing the integrated circuitry formed on the die.
In the past, following testing of a bumped die, it has been necessary to reflow the bumps, which are typically damaged by the test procedure. This is an additional process step that adds to the expense and complexity of the testing process. Furthermore, it requires heating the tested die, which can adversely affect the integrated circuitry formed on the die. U.S. Pat. No. 5,736,456, entitled “METHOD OF FORMING CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATIONS,” describes a technique for forming raised bumps or balls on bond pads of a device under test. An exemplary prior interconnect structure is described in U.S. Pat. No. 5,592,736, entitled “FABRICATING AN INTERCONNECT FOR TESTING UNPACKAGED SEMICONDUCTOR DEVICE HAVING RAISED BOND PADS.”
FIG. 1
illustrates a prior art interconnect structure
10
described in the '736 patent. The interconnect structure
10
includes a substrate
15
with an indentation
20
formed therein. Within the indentation
20
, a series of blades
25
are provided for penetrating the surface of a raised bump (not shown) to establish electrical contact therewith. Other prior art interconnects have used the blade concept to pierce the bond pads of a device under test.
One limitation of the blade technique, is that, over time, material collects between adjacent blades
25
and reduces the reliability of the electrical connection with subsequent devices. In addition additional process steps are required to form the blades
25
and/or the indentation
20
in the bottom of which the blades are formed. Also, the geometry of the previously described interconnect structure
10
does not account for variation in the size of the ball. It is possible that a first ball may contact the interconnect structure
10
, but a second, smaller ball may not be of sufficient size to reach the blades
25
, thus hindering contact.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
An aspect of the present invention is seen in a method for forming an interconnect structure. The method includes providing a substrate, and forming a raised contact member on the substrate. A conductive layer is formed covering at least a portion of the raised contact member. A conductive trace is formed on the substrate in electrical communication with the conductive layer, and an alignment grid is formed on the substrate proximate the raised contact member.
Another aspect of the present invention is seen in an interconnect structure including a substrate and a raised contact member defined in the substrate. A conductive layer covers at least a portion of the raised contact member, and a conductive trace is in electrical communication with the conductive layer. An alignment grid is proximate the raised contact member.


REFERENCES:
patent: 4813129 (1989-03-01), Karnezos
patent: 5370923 (1994-12-01), Goad et al.
patent: 5483741 (1996-01-01), Akram et al.
patent: 5835112 (1998-11-01), Whitlock et al.
patent: 6060778 (2000-05-01), Jeong et al.
patent: 6075710 (2000-06-01), Lau
patent: 6093643 (2000-07-01), Akram

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