Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Ordered or disordered
Reexamination Certificate
1999-05-18
2001-02-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Ordered or disordered
C438S618000, C438S158000, C438S030000, C438S048000, C438S160000, C438S152000, C257S351000, C349S113000
Reexamination Certificate
active
06190936
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a reflective metal surface, and, in particular, to a silicon interconnect passivation and metallization processes designed to maximize reflectance.
2. Description of the Related Art
Liquid crystal displays (LCDs) are becoming increasingly prevalent in high-density projection display devices. These conventional high density projection-type color display devices typically include a light source which emits white light. Dichroic mirrors separate the white light into its corresponding red, green and blue (RGB) bands of light. Each of these colored bands of light is then directed toward a corresponding liquid crystal light valve which, depending with the image to be projected, either permits or prevents transmission of light therethrough. Those RGB bands of light which are permitted to be transmitted through the light valves are then combined by dichroic mirrors or a prism. A projection lens then magnifies and projects the image onto a projection screen.
FIG. 1
illustrates a conventional LCD projection-type imaging system
100
. Imaging system
100
includes a light source
101
. White light is emitted from light source
101
. Once the light hits the prism
103
, the light is separated into its red, green and blue colored bands of light by dichroic filter coatings. Colored light is directed toward liquid crystal display (LCD) light valves
105
. When reflected off light valve
105
, the colored light waves travel back through the prism and through projection lens
107
. Lens
107
magnifies and projects the synthesized color image onto projection screen
109
.
FIG. 2
illustrates a cross-sectional view of adjacent pixel cell structures that form a portion of a conventional light valve. Portion
200
of the conventional light valve includes a glass top plate
202
bonded to an interconnect structure
204
by a sealing member (not shown). The sealing member serves to enclose a display area and to separate glass plate
202
from interconnect
204
by a predetermined minute distance. Thus, the light valve has an inner cavity
206
defined by the glass plate
202
and interconnect
204
. Liquid crystal material
211
, such as polymer dispersed liquid crystal (PDLC), is sealed in inner cavity
206
.
In a reflective mode display technology, an image is generated by creating regions within the light valve having differing contrast. This contrast is created by the state of the liquid crystal material above the reflective surface, which in turn regulates the amount of light passing from the ambient to the reflective surface.
During operation of the light valve shown in
FIG. 2
, selective application of voltage to pixel electrodes
212
a
and
212
b
from underlying capacitor structures
218
a
and
218
b
through metallization
222
and
224
and via
240
switches pixel cells
210
a
and
210
b
on and off. Voltage applied to pixel electrodes
212
a
and
212
b
varies the direction of orientation of the liquid crystal material over the pixel electrode. A change in the direction of orientation of the liquid crystal material at the pixel electrode changes the optical characteristics of the light traveling through the liquid crystal.
If the light valve contains twisted nematic crystal, light passes through the light valve unchanged where no voltage is applied to the pixel electrode, and the light is polarized if a voltage is applied to the pixel electrode. If the light valve contains PDLC, light passes through the light valve unchanged where a voltage is applied to the pixel electrode, and light is scattered if no voltage is applied to the pixel electrode.
One key attribute of light valve performance is the amount of light reflected by the pixel cell. The degree of reflectance of the pixel cell in turn affects other system attributes such as contrast ratio, pixel coherence and brightness efficiency. One approach to enhancing the performance of any reflective mode light valve is to increase the reflectance of the mirror toward the ideal.
In examining
FIG. 2
, it is apparent that pixel electrodes
212
a
and
212
b
will serve as the reflective surface of the light valve. Moreover, the highest (third) intermetal dielectric layer
228
serves as the substrate for the reflective pixel electrodes
212
a
and
212
b.
Therefore, the reflectance of the light value is dependent in large measure on the processing steps which follow formation of the highest intermetal dielectric layer
228
and all subsequent layers.
FIGS. 3A-3L
illustrate cross-sectional views of the conventional processing steps affecting pixel cell reflectance during formation of adjacent pixel cell electrodes.
FIG. 3A
illustrates the formation of TEOS base
328
a
upon lower metallization layer
324
, followed by the formation of SOG layer
328
b
over TEOS base
328
a.
FIG. 3B
illustrates planarization by etchback of SOG
328
b.
FIG. 3C
shows formation of TEOS cap
328
c
over planarized TEOS base
328
a
and SOG
328
b,
forming highest intermetal dielectric layer
328
.
FIG. 3D
illustrates the patterning of a photoresist mask
330
over the planarized surface of highest intermetal dielectric
328
, followed by etching in unmasked areas to create vias
340
.
FIG. 3E
illustrates formation of a liner layer
342
within vias
340
, followed by the formation of a layer of Tungsten
344
over the highest intermetal dielectric
328
, filling vias
340
.
FIG. 3F
illustrates removal of tungsten layer
344
outside of the vias. This step can be accomplished by straight CMP, or alternatively by etchback followed by CMP.
FIG. 3G
illustrates formation of the pixel adhesion underlayer
346
, typically formed from Ti/TiN. This Ti/TiN layer
346
provides an adhesion surface for the AlCu and thereby prevents degradation of reflectance due to roughness occurring during subsequent thermal exposure. The potential contribution of the pixel adhesion layer to loss of reflectance is described in greater detail under Section 4 of the detailed description of the invention.
FIG. 3H
shows formation of the pixel electrode layer
312
on top of pixel adhesion underlayer
346
. Pixel electrode layer
312
is conventionally formed by depositing an Al/Cu mixture at approximately 400° C.
FIG. 3I
illustrates patterning of a photoresist mask
350
on top of pixel electrode layer
312
, followed by etching of unmasked regions of the pixel electrode layer and the pixel adhesion layer
346
to form discrete pixel electrodes
312
a
and
312
b.
FIG. 3J
illustrates removal of patterned photoresist mask
350
from the surface of pixel electrodes
312
a
and
312
b
to complete formation of reflective pixel electrodes
312
a
and
312
b.
Stripping of photoresist mask
350
is conventionally accomplished utilizing a 1) plasma ash, 2) solvent strip, and 3) plasma ash, sequence.
FIG. 3K
illustrates formation of a passivation layer
352
on top of the reflective pixel electrodes
312
a
and
312
b.
This passivation layer
352
(typically silicon dioxide) is deposited at around 400° C. and protects the surface of the pixel electrodes
312
a
and
312
b.
FIG. 3L
illustrates the final alloy/sintering step, wherein a gas mixture including H
2
is diffused through the entire structure at high temperatures. Under these conditions, the H
2
reacts with dangling Si and oxygen bonds at the interface between metal and the underlying silicon, eliminating stray charges that could disrupt the integrity and precision of the silicon-metal contacts.
The high temperatures required during this alloy/sintering step can degrade the reflectance of the pixel cell in several ways. First, exposing the reflective electrode to heat directly reduces its reflectance, as discussed more completely in connection with
FIGS. 19A-19D
and
20
A-
20
C below.
A second source of reflectance loss is growth and movement of metal grains in underlying interconnect metallization layer
324
due to heating. Metal growths
356
formed in metallization layer
324
can in turn disrupt pla
Brown Kevin Carl
Luttrell Richard
Moore Paul McKay
Limbach & Limbach LLP
National Semiconductor Corp.
Smith Matthew
Yevsikov V.
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