Interconnect layout pattern for integrated circuit packages...

Details Interconnect layout pattern for integrated circuit packages... Interconnect layout pattern for integrated circuit packages...

1999-05-18

2001-03-06

Gaffin, Jeffrey (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S777000, C361S795000, C257S691000, C257S773000, C257S778000, C257S786000, C257S728000, C174S261000, C174S262000, C174S266000, C333S012000, C333S247000, C228S180210, C228S180220

Reexamination Certificate

active

06198635

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to integrated circuit device packaging, and more particularly, to the layout of integrated circuit device interconnects for use therein.
BACKGROUND OF THE INVENTION
As integrated circuit devices become faster and more complex, the interconnections between such devices with one another and with other components on a circuit board can limit the performance achievable in an integrated circuit system. Whereas integrated circuit devices, also referred to as “chips”, once had only a few interconnects, often hundreds of interconnects are now required in more complex devices. Forming hundreds of interconnects between a chip and a circuit board, however, can be difficult since chips are typically fabricated with significantly finer details than can be fabricated onto circuit boards. Thus, to connect a fine resolution chip to a circuit board, often some form of packaging is required to route signals between the chip and the circuit board.
The resolution of a component such as a chip or circuit board is often represented in terms of “pitch”, which is the minimum distance between interconnects on a component. For example, chips may have off-chip interconnects separated by 200 microns or less, while a typical circuit board may only be capable of utilizing interconnects separated by 800 to 1000 microns or more. To provide the necessary interface, a chip package is typically used that has a substrate with one side having interconnects disposed at a corresponding pitch for the chip, and with the other side having interconnects disposed at a corresponding pitch for the circuit board. Conductive traces disposed within one or more layers in the package substrate then route the signals between the chip and the circuit board, using vias and/or through holes to route signals between multiple layers. One particular type of interconnect configuration is a ball grid array (BGA), which utilizes an array of metallic balls that interface with a corresponding array of interconnection pads on a circuit board.
Chip packages are often subject to a number of tradeoffs, particularly between performance and cost. Furthermore, the design of a chip package may also impact the performance and cost of the circuit board with which the chip package is used. In particular, system performance is often limited by noise encountered in signals transmitted between a chip package and a circuit board. One predominant form of noise is simultaneously-switching output (SSO) noise that occurs when multiple signals are switching at the same time. Noise often increases as the pitch of interconnects decreases due to the closer proximity of the interconnects. Moreover, reducing the pitch of interconnects can require additional circuit layers on one or both of the chip package and the circuit board to route signals consistent with design rules, which often increases noise due to the presence of longer vias.
Likewise, requiring additional circuit layers in a package and/or circuit board increases costs due to increased complexity, materials and manufacturing costs. In particular, requiring additional layers in a circuit board can dramatically increase the cost of the circuit board.
Traditionally, the layouts of the interconnects between a chip package and a circuit board have diverged into high performance/high cost layouts and low performance/low cost layouts. Some high performance BGA layouts, for example, utilize balls and interconnection pads arranged into a plurality of tiles forming an unchanneled, “chevron” pattern. With a chevron pattern, e.g., as shown by circuit board
10
of
FIG. 9
, columns of alternating power (V) and ground (G) fixed potential interconnection pads
12
,
14
are interposed between pairs of columns of signal (S) interconnection pads
16
, providing a 4:1:1 signal:power:ground interconnect ratio. Each interconnection pad
12
-
16
is then electrically coupled to a via
18
for distribution to another layer in the circuit board. A corresponding layout of balls is provided on the underside of the chip packaging (not shown).
A benefit of the chevron pattern is that electrical performance is often acceptable for high performance applications. A limitation of the chevron pattern, however, is that, at smaller pitches, the ability to route signals away from the array (known as “escape routing”) often requires more layers in the circuit board, which increases costs and decreases performance.
An alternate pattern used in some BGA layouts is a “channeled” pattern, such as shown by circuit board
20
of
FIG. 10
, where power and ground interconnection pads
22
,
24
are paired next to one another such that multiple power/ground interconnection pads can share the same via
26
. Signal interconnection pads
28
are assigned dedicated vias
30
, but with power and ground interconnection pads sharing the same vias, channels such as channel
32
are defined between adjacent columns of signal vias
30
. Through these channels, multiple signal traces can be routed in a given circuit layer, thereby enabling fewer layers to be used, and decreasing costs. However, while a 3:1:1 signal:power:ground ratio of both interconnection pads and balls is provided, the ratio of vias for the channeled pattern is 6:1:1, which results in decreased SSO performance due to a reduction in the number of power and ground vias, and to their non-optimal placement. As a result, the lower cost provided by the channeled pattern comes with reduced performance.
For many applications, electrical performance may not be as great a concern, and as a result, a channeled pattern may be preferred to lower costs. On the other hand, where electrical performance is a concern, a more costly unchanneled pattern may be used. Particularly for chip manufacturers where a given device may be used in widely different applications, it may be necessary to maintain parallel package families to support both high performance/high cost systems and low performance/low cost systems. Maintaining multiple packages, however, often results in additional non-recurring engineering and support costs, and is thus undesirable.
Therefore, a significant need exists for an improved interconnect pattern that better balances cost and performance, and has a wider variety of uses than traditional interconnect patterns.
SUMMARY OF THE INVENTION
The invention addresses these and other problems associated with the prior art by providing a circuit arrangement incorporating unique interconnect layout patterns that are suitable for use in a wide variety of applications. As a result, often a single layout may be used for a particular chip package to support multiple types of applications, thereby offering a more flexible and cost efficient alternative to conventional layouts that are tailored specifically to single applications, e.g., only high performance applications or low performance applications.
Consistent with one aspect of the invention, a circuit arrangement is provided including a plurality of signal interconnects, a plurality of first fixed potential interconnects, and a plurality of second fixed potential interconnects. Each signal interconnect is configured to transmit a signal, while each first fixed potential interconnect is configured to be electrically connected to a first fixed potential (e.g., power), and each second fixed potential interconnect is configured to be electrically connected to a second fixed potential (e.g., ground). The plurality of signal, first fixed potential and second fixed potential interconnects are arranged into at least first and second adjacent tiles, with each tile defining a plurality of interconnect positions arranged into at least three rows and at least four columns. Further, for each tile, a signal interconnect is disposed at each of the three interconnect positions in each of the first and fourth columns, and one each of a signal interconnect, a first fixed potential interconnect and a second fixed potential interconnect are disposed in each of the second and third columns.
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