Interconnect in low-k interlayer dielectrics

Details Interconnect in low-k interlayer dielectrics Interconnect in low-k interlayer dielectrics

2008-06-16

2010-10-12

Dickey, Thomas L (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S508000, C257SE23001

Reexamination Certificate

active

07812455

ABSTRACT:
A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug.

REFERENCES:
patent: 2004/0110369 (2004-06-01), Jiang et al.
patent: 2004/0142557 (2004-07-01), Levy et al.

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