Interconnect for testing semiconductor components and method...

Details Interconnect for testing semiconductor components and method... Interconnect for testing semiconductor components and method...

1999-01-21

2001-06-05

Nguyen, Vinh P. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S755090, C324S754090

Reexamination Certificate

active

06242935

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and specifically to an interconnect for testing semiconductors components such as wafers containing semiconductor dice, and substrates containing semiconductor packages.
BACKGROUND OF THE INVENTION
Semiconductor components can be manufactured using wafer level fabrication processes in which multiple components are contained on a single substrate. Semiconductor dice, for example, are typically fabricated on substrates in the form of silicon wafers. Following the fabrication process, the dice can be singulated into individual units.
Semiconductor packages, such as BGA packages, can also be manufactured using wafer level fabrication processes. A BGA package includes an array of external ball contacts, such as solder balls, that permit the package to be surface mounted to a printed circuit board (PCB) or other electronic component. Some BGA packages have a foot print that is about the size of the die contained in the package. These BGA packages are also known as chip scale packages.
Multiple BGA packages can be fabricated on a single substrate formed of an electrically insulating material. Sometimes the substrate comprises a reinforced polymer laminate, such as bismaleimide triazine (BT), or an epoxy resin (e.g., FR-4). BGA packages can also be fabricated using ceramic or silicon substrates. The substrate can be in the form of a wafer, or in the form of a panel of material.
During, or following, the fabrication process it is usually necessary to perform test procedures on the components to evaluate various electrical characteristics of the components. For example, wafer probe testing can be used to evaluate the gross functionality of dice contained on a wafer.
In order to perform the test procedures it is necessary to make temporary electrical connections with contacts on the components. Semiconductor dice typically include contacts in the form of planar aluminum bond pads, or bond pads bumped with solder bumps. Semiconductor packages typically include contacts in the form of solder balls arranged in a dense area array. For making these temporary electrical connections an interconnect is employed. A wafer probe card is one type of interconnect, and includes probe needles that electrically engage the bond pads on the wafer.
As semiconductor components become smaller, and the contacts on the components become more dense, the temporary electrical connections with the contacts become more difficult to make. Variations in the size and location of the contacts also make the temporary electrical connections difficult to make. In particular, the z-direction location and planarity of contacts can vary between different components on a substrate, and can vary between contacts on the same component. This makes it difficult to make reliable electrical connections with the contacts.
In addition, the contacts can be damaged by the interconnect. Solder balls are particularly susceptible to deformation and loosening of the solder joints that hold the balls on the components. Also, native oxide layers are usually present on the component contacts, and these oxide layers must be penetrated by the contacts on the interconnect. This requires application of forces for scrubbing or penetrating the contacts on the components.
The present invention is directed to an interconnect that can be used to test multiple components contained on a substrate. The interconnect includes contacts that are configured to accommodate dimensional variations, and to accommodate different z-axis locations of the contacts on the components.
SUMMARY OF THE INVENTION
In accordance with the present invention, an interconnect for testing semiconductor components, a test system employing the interconnect, and a method for fabricating the interconnect, are provided. The interconnect is configured to test multiple components contained on a substrate, such as semiconductor dice contained on a wafer, or chip scale packages contained on a panel. In addition, the interconnect can be configured to test semiconductor components having planar contacts, such as bond pads, or to test semiconductor components having ball contacts, such as solder bumps on bumped dice, or solder balls on chip scale packages.
The interconnect, broadly stated, comprises: a substrate; a polymer layer formed on a face of the substrate; a pattern of contacts formed on the polymer layer; and conductive members in the substrate for providing electrical paths from the contacts to external contact pads on a back side of the substrate.
The interconnect substrate comprises an electrically insulating material such as glass reinforced resin, or ceramic, or alternately a semiconducting material, such as silicon. The polymer layer comprises a resilient or compliant material such as polyimide, or a photosensitive polyimide which simplifies the fabrication process The polymer layer provides a resilient or compliant support structure for the interconnect contacts such that movement in the z-direction is possible. This allows the interconnect contacts to move during a test procedure to accommodate differences in the z-axis location, or planarity, of the contacts on the components.
For testing components with planar contacts, the interconnect contacts comprise bumps deposited on conductive layers formed in recesses in the polymer layer. For testing components with ball contacts, the interconnect contacts comprise recesses in the polymer layer covered with conductive layers. In either embodiment the interconnect contacts are in electrical communication with conductive members, which can comprise openings in the interconnect substrate at least partially filled with a conductive material.
The conductive members provide straight line electrical paths from the interconnect contacts to the external contact pads on the back side of the interconnect. The contact pads are configured for electrical engagement by spring loaded electrical connectors (e.g., “POGO PINS”) in electrical communication with test circuitry. In addition to performing an electrical function the spring loaded electrical connectors can also perform a force applying function for biasing the interconnect against the components.
A system constructed in accordance with the invention comprises: a tester having a test head in electrical communication with test circuitry; a probe card mounted to the test head; an interconnect mounted to the probe card; a force applying mechanism having spring loaded electrical connectors in electrical communication with the test circuitry and adapted to press the interconnect against the components; and a wafer chuck for supporting and aligning the components to the interconnect.


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