Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-10-29
2001-12-25
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000, C257S780000, C257S781000, C257S692000, C438S612000, C438S613000
Reexamination Certificate
active
06333555
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and more particularly to an interconnect for making electrical connections with semiconductor components.
BACKGROUND OF THE INVENTION
Semiconductor dice are used in the construction of electronic components, such as multi chip modules. For example, bare semiconductor dice can be mounted to substrates formed of ceramic and FR-4 materials. Flip chip mounting of bumped dice is one method for electrically connecting the dice to the substrates. With flip chip mounting, solder bumps on the device bond pads are reflowed into electrical contact with contacts on the substrate. Chip on board (COB) mounting of dice to substrates can also be employed. With chip on board mounting, wire bonds are formed between the device bond pads and contacts on the substrate. TAB mounting is another mounting method. With TAB mounting, electrical connections are made to the device bond pads, using a multi layer tape comprising a polymer backing with patterns of conductors.
Chip scale packages are sometimes used in place of bare dice for fabricating electronic components. Typically, a chip scale package includes a substrate bonded to the face of a bare die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. The substrate for a chip scale package can comprise a flexible material, such as a polymer tape, or a rigid material, such as silicon, ceramic, glass or FR-4. The external contacts for one type of chip scale package include solder balls arranged in a dense array, such as a ball grid array (BGA), or a fine ball grid array (FBGA). In general, chip scale packages can be mounted to substrates using the same mounting methods employed with bare dice (e.g., flip chip, COB, TAB).
Besides making permanent electrical connections to bare dice and chip scale packages for fabricating electronic components, electrical connections are sometimes necessary for testing applications. For example, bare dice are tested in the manufacture of known good die (KGD). Chip scale packages must also be tested prior to use in electronic components. In these cases the electrical connections with the device bond pads for bare dice, or with external contacts for chip scale packages, are preferably non-bonded, temporary electrical connections. In addition to being temporary, the electrical connections must have a low contact resistance, and preferably cause minimal damage to the device bond pads or external contacts.
The present invention is directed to an improved interconnect for making electrical connections with semiconductor components including dice and chip scale packages.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved interconnect for semiconductor components, such as dice, wafers and chip scale packages, and a method for fabricating the interconnect are provided. Also provided are improved test systems employing the interconnect.
The interconnect includes a substrate, and polymer contact members formed on the substrate, adapted to electrically engage contacts on the components. The polymer contact members also include conductive layers in electrical communication with conductors formed on the substrate.
The substrate comprises a rigid material such as ceramic, amorphous silicon, polycrystalline silicon, monocrystalline silicon, or a glass filled resin. The polymer contact members comprise a thick film resist, which is deposited on the substrate, photopatterned, etched, and then cured. One suitable thick film resist is a negative tone resist comprising an epoxy resin, an organic solvent, and a photo initiator. The thick film resist is capable of forming contact members with a high aspect ratio, in which a height, or depth, of the contact members is much greater than a width, or diameter, of the contact members. The conductive layers for the contact members comprise a metal, such as nickel, palladium, or platinum, deposited with a low temperature process, such as electrolyses deposition or electrochemical deposition.
In an illustrative embodiment, the polymer contact members are raised members with penetrating projections adapted to penetrate contacts on the components to a limited penetration depth. In this embodiment, the contact members can be used to electrically contact either planar contacts (e.g., bond pads) on the components, or to electrically contact bumped contacts (e.g., solder balls) on the components. In an alternate embodiment, the polymer contact members are indentations adapted to retain and electrically engage bumped contacts on the components. In this embodiment, penetrating projections with a high aspect ratio can be formed in the indentations for penetrating the bumped contacts.
The method for fabricating the interconnect includes the steps of: providing a substrate; depositing a thick film polymer layer on the substrate; patterning the polymer layer; etching the polymer layer to form contact members; curing the polymer layer to harden the contact members; forming conductive layers on the contact members; and then forming conductors on the substrate in electrical communication with the contact members.
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Akram Salman
Farnworth Warren M.
Gratton Stephen A.
Lee Eddie
Lee Eugene
Micro)n Technology, Inc.
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