Interconnect exhibiting reduced parasitic capacitance variation

Details Interconnect exhibiting reduced parasitic capacitance variation Interconnect exhibiting reduced parasitic capacitance variation

1999-10-28

2002-07-02

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With contact or metallization configuration to reduce...

C257S758000

Reexamination Certificate

active

06414367

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure and process for reducing variation in interconnect parasitic capacitance, and in particular, to a process and apparatus utilizing insertion of a third metal line between adjacent metal lines to reduce interconnect parasitic capacitance variation.
2. Description of the Related Art
The ever-decreasing feature size of semiconductor devices, and the corresponding increase in packing density, has rendered integrated circuits (IC's) more sensitive than ever to signal propagation delays. At this advanced phase of IC development, IC operation is limited by the delay in propagation of signals between active devices of the circuit, rather than by the speed of the semiconducting devices themselves.
Propagation delay is determined in large part by parasitic resistive-capacitive (RC) delay caused by interconnect linking together various devices of the IC. The magnitude of this RC delay is in turn determined in large measure by the parasitic capacitance (C
PAR
) component.
In designing IC's, engineers can and do take parasitic capacitance into account. However, this task is complicated by the fact that interconnect parasitic capacitance varies between maximum and minimum values. Therefore, the engineer must ensure that the IC can function over the entire range of variation in interconnect parasitic capacitance.
One important source of variation in interconnect parasitic capacitance is the variation in critical dimension (CD) of adjacent metal lines of an interconnect metallization layer. This is illustrated in
FIGS. 1A-1C
.
FIG. 1A
shows a cross-sectional view of an interconnect
100
featuring interconnect metallization layer
102
including adjacent first and second metal lines
102
a
and
102
b
respectively. Metal lines
102
a
and
102
b
are positioned over lower interlayer dielectric (ILD)
104
. First and second metal lines
102
a
and
102
b
are formed by patterning a photoresist mask over interconnect metallization layer
102
, and then etching interconnect metallization layer
102
in unmasked areas to stop on underlying lower ILD
104
. Next, a second interlayer dielectric
106
is formed over the entire surface, such that dielectric material
106
penetrates into inter-line region
108
between metal lines
102
a
and
102
b.
Parasitic capacitance arising between first metal line
100
a
and second metal line
100
b
obeys the following equation:
C
PAR
=(∈
S
)/
d,
where
C
PAR
=parasitic capacitance;
∈=dielectric permittivity;
S=area of the plates of the capacitor; and
d=distance between the adjacent metal lines.
Variation in interconnect parasitic capacitance can be introduced during fabrication of the interconnect structure. One source of parasitic capacitance variation occurs during photolithography leading to formation of the metal lines. Specifically, variation in width of the patterned photoresist mask can in turn induce variation in parasitic capacitance.
This is illustrated by
FIGS. 1B and 1C
, which also depict cross-sectional views of adjacent metal lines of an interconnect metallization layer.
In
FIG. 1B
, variation in photolithographic processing has led to formation of adjacent metal lines
102
a
and
102
b
possessing a width narrower than that of the adjacent metal lines depicted in FIG.
1
A. Because of this changed critical dimension, the distance between adjacent metal lines
102
a
and
102
b
is increased. And, as a direct consequence of Equation (I), the corresponding parasitic capacitance is reduced.
Conversely,
FIG. 1C
shows a cross-sectional view of adjacent metal lines of an interconnect metallization layer wherein photolithographic processing has created metal lines
102
a
and
102
b
wider than the adjacent metal lines of FIG.
1
A. As a result of this changed critical dimension, the distance between adjacent metal lines
102
a
and
102
b
is decreased, and the corresponding parasitic capacitance is increased.
The relation between variation in critical dimension and interconnect parasitic capacitance is shown in FIG.
2
.
FIG. 2
plots variation in critical dimension (&Dgr;CD) versus parasitic capacitance (C
PAR
).
FIG. 2
shows that &Dgr;CD introduces a spectrum of possible parasitic capacitances into an interconnect structure. This capacitance variation C
VAR
ranges between a minimum capacitance (C
MIN
) wherein &Dgr;CD is a negative value (and adjacent metal lines are narrow), and a maximum capacitance (C
MAX
) wherein &Dgr;CD is a positive value (and adjacent metal lines are wide).
Because variation in parasitic interconnect capacitance governs anticipated signal propagation delay and thereby confines design of IC's, there is a need in the art for an interconnect structure and a process for forming an interconnect structure wherein variation in parasitic interconnect capacitance is minimized.
SUMMARY OF THE INVENTION
The present invention relates to an interconnect structure and a process for forming an interconnect structure, in which variation in parasitic capacitance is reduced. This variation reduction is accomplished by interposing a third metal line between adjacent metal lines of an interconnect metallization layer. The third metal line is in electrical communication with one of the adjacent metal lines. By projecting the third metal line between the adjacent metal lines, variation in parasitic capacitance is reduced over a range of critical dimensions.
An embodiment of a process for forming an interconnect structure in accordance with the present invention comprises the steps of forming a lower interlayer dielectric over a semiconductor workpiece and forming an interconnect metallization layer over the lower interlayer dielectric. A photoresist mask is patterned over the interconnect metallization layer, the photoresist including a masked region having a critical dimension and excluding an unmasked region. The interconnect metallization layer is etched in the unmasked region to leave a first metal line separated from a second metal line by an inter-line region, a width of the first and second metal lines corresponding to the critical dimension, the first and second metal lines exhibiting a parasitic capacitance. A conformal middle interlayer dielectric is formed over the first and second metal lines and over the lower interlayer dielectric in the inter-line region. A third metal line is formed over the conformal middle interlayer dielectric, the third metal line electronically linked with the first metal line and projecting between the first and second metal lines in the inter-line region to elevate the parasitic capacitance and thereby reduce an overall variation in parasitic capacitance over a range of critical dimensions.
An embodiment of an interconnect structure in accordance the present invention comprises a lower interlayer dielectric positioned over a semiconductor workpiece, a first metal line formed over the lower interlayer dielectric, and a second metal line formed over the lower interlayer dielectric and separated from the first metal line by an inter-line region. A middle interlayer dielectric covers the first and second metal lines and the lower interlayer dielectric in the inter-line region. A third metal line projects between the first and second metal lines and is separated from the first and second metal lines by the middle interlayer dielectric, the third metal line in electrical communication with one of the first and the second metal lines.
The features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.


REFERENCES:
patent: 5128737 (1992-07-01), van der Have
patent: 5635753 (1997-06-01), Hofflinger et al.
patent: 5734187 (1998-03-01), Bohr et al.
patent: 6084304 (2000-07-01), Huang et al.
patent: 11-352512 (1999-12-01), None
Wolf, S., “Silicon Processing for the VLSI Era”, vol. 2, Process Integration, pp. 183-186 1990 (No month given).

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