Interconnect design with controlled inductance

Details Interconnect design with controlled inductance Interconnect design with controlled inductance

1996-06-27

2000-07-11

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257532, 257691, 257203, H01L 2348, H01L 2352, H01L 2940

Patent

active

060877286

ABSTRACT:
An integrated circuit device interconnect with controlled inductance. An integrated circuit device includes an insulating layer formed on a substrate and a an interconnect disposed on the insulating layer extending along a first path. A dedicated current return path having one end configured to be coupled to ground is disposed on the first insulating layer parallel to the interconnect, such that the signal received by the interconnect is returned to ground via the dedicated current return path when the dedicated current return path is coupled to ground. Inductance of the interconnect is thus controlled by reducing the area of the circuit loop formed by the interconnect and the parallel dedicated current return path. In one embodiment, the dedicated current return path is formed in an embedded ground plane just above or below the first interconnect. In this embodiment, the interconnect and the dedicated current return path together act as a built-in decoupling capacitor, further offsetting the inductive time constant to approach critical damping.

REFERENCES:
patent: 5025304 (1991-06-01), Reisman et al.
patent: 5287002 (1994-02-01), Freeman, Jr. et al.
patent: 5402318 (1995-03-01), Otsuka et al.
patent: 5439848 (1995-08-01), Hsu et al.
patent: 5471091 (1995-11-01), Pasch et al.
patent: 5544103 (1996-08-01), Lambertson
patent: 5585664 (1996-12-01), Ito
patent: 5631478 (1997-05-01), Okumura
patent: 5719439 (1998-02-01), Iwasaki et al.
patent: 5723908 (1998-05-01), Fuchida et al.

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