Interconnect delay calculation apparatus and path delay value ve

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G06F 1750

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058751149

ABSTRACT:
A circuit model is used which consists essentially of a common portion having an interconnect wire length percentage of A %, and a branch portion having an interconnect wire length percentage of (100-A) % and branched uniformly for each fan-out (n). An interconnect delay calculation apparatus calculates estimated interconnect delay values using data of a coefficient (A) previously determined for each fan-out (n) from past design data by a statistical technique on the basis of a delay calculation expression for the circuit model which is {A/100+(100-A)/(100n.sup.2)}Rw(Cw+Cp). The estimated interconnect delay values are calculated accurately when a semiconductor integrated circuit is designed.

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On-Line Manual, Ver. 3.4a, U.S. Synopsys Company, Library Compiler Reference vol. 1, pp. 4.9-4.12.

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