Interconnect delay calculation apparatus and path delay value ve

Details Interconnect delay calculation apparatus and path delay value ve Interconnect delay calculation apparatus and path delay value ve

1997-02-13

1999-02-23

Teska, Kevin J.

Boots, shoes, and leggings

G06F 1750

Patent

active

058751149

ABSTRACT:
A circuit model is used which consists essentially of a common portion having an interconnect wire length percentage of A %, and a branch portion having an interconnect wire length percentage of (100-A) % and branched uniformly for each fan-out (n). An interconnect delay calculation apparatus calculates estimated interconnect delay values using data of a coefficient (A) previously determined for each fan-out (n) from past design data by a statistical technique on the basis of a delay calculation expression for the circuit model which is {A/100+(100-A)/(100n.sup.2)}Rw(Cw+Cp). The estimated interconnect delay values are calculated accurately when a semiconductor integrated circuit is designed.

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patent: 5617325 (1997-04-01), Schaefer et al.
patent: 5629860 (1997-05-01), Jones et al.
patent: 5666290 (1997-09-01), Li et al.
patent: 5790415 (1998-08-01), Pullela et al.
On-Line Manual, Ver. 3.4a, U.S. Synopsys Company, Library Compiler Reference vol. 1, pp. 4.9-4.12.

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