Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2001-02-05
2003-06-10
Sircus, Brian (Department: 2839)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C439S071000
Reexamination Certificate
active
06575765
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to electrical interconnects. More particularly, this invention relates to an interconnect assembly and method for a semiconductor device, in which the interconnect assembly can be used in lieu of wirebond connections to form an electronic assembly.
BACKGROUND OF THE INVENTION
Wire bonding is a method well known in the art for making electrical connections to semiconductor devices. The technique typically entails the use of very thin electrically-conductive wires, often of aluminum or gold, which are bonded to bond pads on a device and conductors on a surface of the substrate to which the device is mounted. Suitable wire bonds can be achieved with various techniques, including thermosonic bonding and ultrasonic bonding. While widely used in the art, wire bonding has shortcomings. For example, wire interconnects are limited by the amount of current that the wires can carry, which is primarily a function of the cross-sectional area and electrical conductivity of the wire. Furthermore, the die geometries of certain semiconductor devices do not allow for multiple wire bonds, and wire bonds can be susceptible to fatigue failures caused by thermal cycling and fusing due to high current. The wire bond operation is also relatively time consuming, and therefore undesirable as the interconnect method for devices requiring a large number of interconnects. Making many ultrasonic wirebonds to a semiconductor device is also complicated by the risk of damage to the device. While statistical process control (SPC) of bond strengths using pull test data has been successfully employed to minimize some of the above shortcomings, alternative interconnect methods are continuously sought for applications where wire bonding and other conventional interconnect techniques are not well suited.
SUMMARY OF THE INVENTION
The present invention is directed to an interconnect assembly and method for a semiconductor device, in which the interconnect assembly can be used in lieu of wirebond connections to form an electronic assembly. Generally, the interconnect assembly includes first and second interconnect members. The first interconnect member has a first surface with a first contact and a second surface with a second contact electrically connected to the first contact, while the second interconnect member has a flexible finger adapted for contacting the second contact of the first interconnect member. The first interconnect member is adapted to be aligned and registered with a semiconductor device having a contact on a first surface thereof so that the first contact of the first interconnect member electrically contacts the contact of the semiconductor device. Consequently, the method of assembling an electronic assembly enabled by the present invention does not require any wirebonds, but instead merely entails aligning and registering the first interconnect member with the semiconductor device so that the contacts of the first interconnect member and the semiconductor device make electrical contact, and then contacting the second contact of the first interconnect member with the flexible finger of the second interconnect member. The first interconnect member is preferably configured to be self-aligning with the semiconductor device to facilitate the assembly process.
As described above, the interconnect assembly and method of this invention can be readily modified to include additional interconnect members similar to the first and/or second interconnect members. In addition, the first interconnect member (and any additional interconnect members similar thereto) may have multiple contacts on opposite surfaces, and the second interconnect member (and any additional interconnect members similar thereto) may have multiple fingers so that multiple interconnections can be simultaneously made to multiple contacts on a semiconductor device. The first and second interconnect members can also be used to make simultaneous electrical interconnects to any number of semiconductor devices of various types. These advantages of the invention are achieved with interconnect members that can be readily configured to avoid the various shortcomings noted for wirebonds, including limited current capacity, difficulties in simultaneously making interconnects with multiple contacts on certain die geometries, and susceptibility to fatigue failures caused by thermal cycling and fusing due to high current. In addition, the interconnect method is much less time consuming than conventional wire-bonding operations, and can be accomplished to produce a large number of interconnects to a semiconductor device with minimal risk of damage to the device.
Other objects and advantages of this invention will be better appreciated from the following detailed description.
REFERENCES:
patent: 5173205 (1992-12-01), Grabbe
patent: 5455459 (1995-10-01), Fillion et al.
patent: 5772451 (1998-06-01), Dozier, II et al.
patent: 5939739 (1999-08-01), O'Keefe
Delphi Technologies Inc.
Funke Jimmy L.
Prashad Chandrika
Sircus Brian
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