Interconnect and driver optimization for high performance proces

Details Interconnect and driver optimization for high performance proces Interconnect and driver optimization for high performance proces

1995-06-30

1997-07-15

Teska, Kevin J.

H03H 1126

Patent

active

056491700

ABSTRACT:
A method for determining an optimal design for wiring interconnect and driver power for a designed target delay begins at the floor planning stages of the chip design and may be repeated during the design process. The designer initially specifies a maximum width that wires are allowed to use and a target delay value. Then the designer gives values to weights used in the calculation of an optimization function G(d,p,w), where d is the delay, p is the power, and w is wire width. An "ideal" slope ##EQU1## is calculated, assuming zero resistance. The designer chooses a slope decrease value from the "ideal" slope value. For each set wire width, the delay (at the proper slope) belonging to that particular wire width is obtained. With these inputs, an optimization program according to the invention is run. This program then calculates values of the function G(d,p,w) for increasing wire pitches, starting with the minimum allowed by the technology. The process continues until (1) the target delay is set by the designer is met, (2) the largest pitch value allowed by the designer is reached, or (3) further calculation will not yield a smaller value for the optimization function.

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Menezes, Noel and Lawrence Pillage. Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. submitted for publication Feb. 2, 1995.
Zhou et al., Interconnection Delay in Very High-Speed VLSI IEEE Transactions on Circuits and Systems, vol. 38, No. 7, Jul. 1991.

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