Interconnect and carrier with resistivity measuring contacts...

Details Interconnect and carrier with resistivity measuring contacts... Interconnect and carrier with resistivity measuring contacts...

1999-06-28

2001-10-02

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S715000, C324S765010, C324S754090

Reexamination Certificate

active

06297653

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor testing, and specifically to a test interconnect, a test method, a test carrier and a test system for testing semiconductor components, such as bare dice and packages.
BACKGROUND OF THE INVENTION
Different types of semiconductor components are tested following the fabrication process. Test systems have been developed for applying test signals to the integrated circuits contained on the components. For example, discrete semiconductor components, such as bare dice and chip scale packages, are tested using carriers designed to temporarily package one or more components. These components include terminal contacts which provide electrical connection points for applying the test signals. For example, bare dice can include terminal contacts, such as planar or bumped bond pads. Chip scale packages can include terminal contacts such as solder balls in a dense grid array.
The test systems include an interconnect that makes the temporary electrical connections with the terminal contacts on the components. This type of interconnect includes contacts that physically and electrically engage the terminal contacts on the component. For example, U.S. Pat. No. 5,686,317 entitled “METHOD FOR FORMING AN INTERCONNECT HAVING A PENETRATION LIMITED CONTACT STRUCTURE FOR ESTABLISHING A TEMPORARY ELECTRICAL CONNECTION WITH A SEMICONDUCTOR DIE”, describes an interconnect configured for testing bare dice having planar contacts. U.S. Pat. No. 5,592,736 entitled “FABRICATING AN INTERCONNECT FOR TESTING UNPACKAGED SEMICONDUCTOR DICE HAVING RAISED BOND PADS” describes an interconnect for testing bare dice having bumped contacts.
One problem with the electrical connections between the terminal contacts on the component, and the mating contacts on the interconnect, occurs when oxide layers, or other contaminants, are present on the mating surfaces. For example, aluminum oxide layers can develop on planar aluminum bond pads, and solder oxide layers can develop on exposed surfaces of solder balls. Particulate contaminants such as dust, and other particles, can also be present on the component contacts. These native oxide layers and contaminants can adversely affect the test results, by increasing the resistivity of the temporary electrical connections.
Similarly, the contacts on the interconnect can develop native oxide layers. For this reason the interconnect contacts are sometimes formed of a non-oxidizing material, such as Ti, Pt, Au or TiS
2
. However, the interconnects are reusable, and the interconnect contacts can be used to test thousands of components over a period of months. Accordingly, contaminants can adhere to the interconnect contacts, increasing the resistivity of the temporary electrical connections with the component contacts. Also, the resistivity, as well as other electrical characteristics of the interconnect contacts, can change with continued use due to deformation of the contacts.
It would be advantageous for an interconnect to have the capability to measure the resistivity of the temporary electrical connections with the terminal contacts on the components. This would permit the test signals to be adjusted in accordance with the measured resistivity. The present invention is directed to an interconnect, test carrier and test system configured to measure the resistivity of the temporary electrical connections between the interconnect and component.
SUMMARY OF THE INVENTION
In accordance with the present invention, a test interconnect, a test method, a test carrier, and a test system for testing semiconductor components, are provided.
The interconnect includes a substrate, and a plurality of interconnect contacts on the substrate for electrically engaging terminal contacts on the components. The interconnect contacts can be configured to electrically engage either planar component contacts (e.g., bond pads, test pads, land pads), or bumped component contacts (e.g., solder balls, metal bumps, conductive polymer bumps). For engaging planar contacts, the interconnect contacts can comprise etched members with projections for penetrating the planar contacts to a limited penetration depth. For engaging bumped contacts, the interconnect contacts can comprise recesses sized and shaped to retain the bumped contacts, or alternately projections configured to penetrate the bumped contacts.
At least one pair of the interconnect contacts comprise resistivity contacts. The resistivity contacts are in electrical communication with test pads configured as a four terminal Kelvin structure. The resistivity contacts and test pads can be used with a resistivity measuring circuit, to determine a contact resistance between the resistivity contacts and interconnected terminal contacts on a component under test. In an illustrative embodiment, the resistivity contacts electrically engage interconnected pairs of power (Vcc), or ground (Vss) terminal contacts on the component, such that an electrical path between the resistivity contacts is provided through the component.
The resistivity measuring circuit evaluates a total resistance Rx of the electrical path between the resistivity contacts. A contact resistance Rc between the resistivity contacts on the interconnect, and the interconnected terminal contacts on the component, forms a portion of the total resistance Rx. The total resistance Rx can be bench marked by testing the interconnect prior to use, or immediately following a cleaning. Using this bench mark, the contact resistance Rc can be quantified using resistivity measurements performed during testing. A high value for the contact resistance Rc can indicate the presence of thick metal oxides or contaminants on the contacts, or can indicate misaligned or damaged contacts.
The resistivity measuring circuit includes two impedance sense terminals, and two impedance source terminals which can be placed in electrical communication with the four terminal Kelvin structure on the interconnect. With this arrangement, test currents can be applied through known resistances RL to the resistivity contacts. In addition, sense currents can be applied through known resistances RL to the resistivity contacts. The sense currents are very low (e.g., pico-amps) such that the I-R drops are low, and the voltage seen by sense terminals is the same as the voltage developed across the resistivity contacts. This enables a total resistance Rx of the electrical path between the resistivity contacts to be measured.
During a test method performed in accordance with the invention, the resistivity measurements can be used to provide feed back for adjusting test signal voltages and currents. The test method includes the steps of analyzing the resistivity measurements, and then controlling test signals as a function of the resistivity measurements. The resistivity measurements can also be used to indicate that the interconnect or the component requires cleaning. In this case the test method can include the step of notifying an operator, or automated tester of the test system, of high values for the resistivity measurements.
The test carrier includes the interconnect, and is configured to retain a component under test. The test carrier also includes a base wherein the interconnect is mounted, and a force applying mechanism for biasing the component against the interconnect. The test system includes multiple interconnects, and force applying mechanisms, mounted to a test board.


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patent: 5519332 (1996-05-01), Wood et al.
patent: 5559444 (1996-09-01), Farnwort

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