Patent
1991-10-07
1992-08-25
Shaw, Gareth D.
395200, 395275, 395325, 3952285, 3952288, 3952292, 3952401, 3952411, 3952417, G06F 1314
Patent
active
051426838
ABSTRACT:
Interprocessor message communication and synchronization apparatus and method for a plurality of processors connected to a system bus. The message communication photocol involves utilizing an array of mailbox locations associated with the processors, respectively, and located in common memory accessible to all of the processors. A processor desiring to send a message to another processor inserts the message into its mailbox along with the address of the other processor. The sending processor interrupts the receiving processor which, in response to the interrupt, scans the mailboxes to find the mailbox with its address therein thereby receiving the message. The interrupt is effected by the sending processor broadcasting an input/output write instruction on the system bus along with the address of the receiving processor and a data field representative of the interrupt to be transmitted. Apparatus associated with the receiving processor includes a decoder that responds to the input/output write instruction to enable a register when the address transmitted on the bus matches its address. The enabled register receives the data signals from the bus to set therein the appropriate interrupt signal represented by the data. The stages of the register are connected to the associated interrupt input of the other processor.
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Bermond-Gregoire Patrice M. A.
Burkhardt, Jr. Kenneth J.
Gerbehy Jay L.
Skapinetz Theodore J.
Cooper Albert B.
Loomis John C.
Shaw Gareth D.
Starr Mark T.
Unisys Corporation
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